Analytic Approach to the Operation of RTD Ternary Inverters Based on MML

Open Access.Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.This work has been funded by the Spanish Government under project NDR, TEC2007- 67245/MIC, and the Junta de Andalucía through the Proyecto de Excelencia TIC-2961.Peer Reviewe

The implementation and applications of multiple-valued logic

Multiple-Valued Logic (MVL) takes two major forms. Multiple-valued circuits can implement the logic directly by using multiple-valued signals, or the logic can be implemented indirectly with binary circuits, by using more than one binary signal to represent a single multiple-valued signal. Techniques such as carry-save addition can be viewed as indirectly implemented MVL. Both direct and indirect techniques have been shown in the past to provide advantages over conventional arithmetic and logic techniques in algorithms required widely in computing for applications such as image and signal processing. It is possible to implement basic MVL building blocks at the transistor level. However, these circuits are difficult to design due to their non binary nature. In the design stage they are more like analogue circuits than binary circuits. Current integrated circuit technologies are biased towards binary circuitry. However, in spite of this, there is potential for power and area savings from MVL circuits, especially in technologies such as BiCMOS. This thesis shows that the use of voltage mode MVL will, in general not provide bandwidth increases on circuit buses because the buses become slower as the number of signal levels increases. Current mode MVL circuits however do have potential to reduce power and area requirements of arithmetic circuitry. The design of transistor level circuits is investigated in terms of a modern production technology. A novel methodology for the design of current mode MVL circuits is developed. The methodology is based upon the novel concept of the use of non-linear current encoding of signals, providing the opportunity for the efficient design of many previously unimplemented circuits in current mode MVL. This methodology is used to design a useful set of basic MVL building blocks, and fabrication results are reported. The creation of libraries of MVL circuits is also discussed. The CORDIC algorithm for two dimensional vector rotation is examined in detail as an example for indirect MVL implementation. The algorithm is extended to a set of three dimensional vector rotators using conventional arithmetic, redundant radix four arithmetic, and Taylor's series expansions. These algorithms can be used for two dimensional vector rotations in which no scale factor corrections are needed. The new algorithms are compared in terms of basic VLSI criteria against previously reported algorithms. A pipelined version of the redundant arithmetic algorithm is floorplanned and partially laid out to give indications of wiring overheads, and layout densities. An indirectly implemented MVL algorithm such as the CORDIC algorithm described in this thesis would clearly benefit from direct implementation in MVL

Cutting Edge Nanotechnology

The main purpose of this book is to describe important issues in various types of devices ranging from conventional transistors (opening chapters of the book) to molecular electronic devices whose fabrication and operation is discussed in the last few chapters of the book. As such, this book can serve as a guide for identifications of important areas of research in micro, nano and molecular electronics. We deeply acknowledge valuable contributions that each of the authors made in writing these excellent chapters

The 1992 4th NASA SERC Symposium on VLSI Design

Papers from the fourth annual NASA Symposium on VLSI Design, co-sponsored by the IEEE, are presented. Each year this symposium is organized by the NASA Space Engineering Research Center (SERC) at the University of Idaho and is held in conjunction with a quarterly meeting of the NASA Data System Technology Working Group (DSTWG). One task of the DSTWG is to develop new electronic technologies that will meet next generation electronic data system needs. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The NASA SERC is proud to offer, at its fourth symposium on VLSI design, presentations by an outstanding set of individuals from national laboratories, the electronics industry, and universities. These speakers share insights into next generation advances that will serve as a basis for future VLSI design

Increased lifetime of Organic Photovoltaics (OPVs) and the impact of degradation, efficiency and costs in the LCOE of Emerging PVs

Emerging photovoltaic (PV) technologies such as organic photovoltaics (OPVs) and perovskites (PVKs) have the potential to disrupt the PV market due to their ease of fabrication (compatible with cheap roll-to-roll processing) and installation, as well as their significant efficiency improvements in recent years. However, rapid degradation is still an issue present in many emerging PVs, which must be addressed to enable their commercialisation. This thesis shows an OPV lifetime enhancing technique by adding the insulating polymer PMMA to the active layer, and a novel model for quantifying the impact of degradation (alongside efficiency and cost) upon levelized cost of energy (LCOE) in real world emerging PV installations. The effect of PMMA morphology on the success of a ternary strategy was investigated, leading to device design guidelines. It was found that either increasing the weight percent (wt%) or molecular weight (MW) of PMMA resulted in an increase in the volume of PMMA-rich islands, which provided the OPV protection against water and oxygen ingress. It was also found that adding PMMA can be effective in enhancing the lifetime of different active material combinations, although not to the same extent, and that processing additives can have a negative impact in the devices lifetime. A novel model was developed taking into account realistic degradation profile sourced from a literature review of state-of-the-art OPV and PVK devices. It was found that optimal strategies to improve LCOE depend on the present characteristics of a device, and that panels with a good balance of efficiency and degradation were better than panels with higher efficiency but higher degradation as well. Further, it was found that low-cost locations were more favoured from reductions in the degradation rate and module cost, whilst high-cost locations were more benefited from improvements in initial efficiency, lower discount rates and reductions in install costs

Polarity Control at Runtime:from Circuit Concept to Device Fabrication

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to overcome physical limitations affecting conventional CMOS technology. Here, we propose a novel Schottky barrier device concept based on electrostatic polarity control. Specifically, this device can behave as p- or n-type by simply changing an electric input bias. This device combines More-than-Moore and Beyond CMOS elements to create an efficient technology with a viable path to Very Large Scale Integration (VLSI). This thesis proposes a device/circuit/architecture co-optimization methodology, where aspects of device technology to logic circuit and system design are considered. At device level, a full CMOS compatible fabrication process is presented. In particular, devices are demonstrated using vertically stacked, top-down fabricated silicon nanowires with gate-all-around electrode geometry. Source and drain contacts are implemented using nickel silicide to provide quasi-symmetric conduction of either electrons or holes, depending on the mode of operation. Electrical measurements confirm excellent performance, showing Ion/Ioff > 10^7 and subthreshold slopes approaching the thermal limit, SS ~ 60mV/dec (~ 63mV/dec) for n(p)-type operation in the same physical device. Moreover, the shown devices behave as p-type for a polarization bias (polarity gate voltage, Vpg) of 0V, and n-type for a Vpg = 1V, confirming their compatibility with multi-level static logic circuit design. At logic gate level, two- and four-transistor logic gates are fabricated and tested. In particular, the first fully functional, two-transistor XOR logic gate is demonstrated through electrical characterization, confirming that polarity control can enable more compact logic gate design with respect to conventional CMOS. Furthermore, we show for the first time fabricated four- transistors logic gates that can be reconfigured as NAND or XOR only depending on their external connectivity. In this case, logic gates with full swing output range are experimentally demonstrated. Finally, single device and mixed-mode TCAD simulation results show that lower Vth and more optimized polarization ranges can be expected in scaled devices implementing strain or high-k technologies. At circuit and system level, a full semi-custom logic circuit design tool flow was defined and configured. Using this flow, novel logic libraries based on standard cells or regular gate fabrics were compared with standard CMOS. In this respect, results were shown in comparison to CMOS, including a 40% normalized area-delay product reduction for the analyzed standard cell libraries, and improvements of over 2× in terms of normalized delay for regular Controlled Polarity (CP)-based cells in the context of Structured ASICs. These results, in turn, confirm the interest in further developing and optimizing CP devices, as promising candidates for future digital circuit technology

Design of resonant-tunneling diodes for a GaAs integrated SRAM

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (p. 173-178).by Rajni J. Aggarwal.Ph.D

Process development using oscillatory baffled mesoreactors

PhD ThesisThe mesoscale oscillatory baffled reactor (meso-OBR) is a flow chemistry platform whose niche is the ability to convert long residence time batch processes to continuous processes. This reactor can rapidly screen reaction kinetics or optimise a reaction in flow with minimal waste. In this work, several areas were identified that could be addressed to broaden the applicability of this platform. Four main research themes were subsequently formulated and explored: (I) development of deeper understanding of the fluid mechanics in meso-OBRs, (II) development of a new hybrid heat pipe meso-OBR for improved thermal management, (III) further improvement of continuous screening using meso-OBRs by removing the solvent and employing better experiment design methodologies, and (IV) exploration of 3D printing for rapid reactor development. I. The flow structures in a meso-OBR containing different helical baffle geometries were studied using computational fluid dynamics simulations, validated by particle image velocimetry (PIV) experiments for the first time. It was demonstrated, using new quantification methods for the meso-OBR, that when using helical baffles swirling is responsible for providing a wider operating window for plug flow than other baffle designs. Further, a new flow regime resembling a Taylor-Couette flow was discovered that further improved the plug flow response. This new double vortex regime could conceivably improve multiphase mixing and enable flow measurements (e.g. using thermocouples inside the reactor) to be conducted without degrading the mixing condition. This work also provides a new framework for validating simulated OBR flows using PIV, by quantitatively comparing turbulent flow features instead of qualitatively comparing average velocity fields. II. A new hybrid heat pipe meso-OBR (HPOBR) was prototyped to provide better thermal control of the meso-OBR by exploiting the rapid and isothermal properties of the heat pipe. This new HPOBR was compared with a jacketed meso-OBR (JOBR) for the thermal control of an exothermic imination reaction conducted without a solvent. Without a solvent or thermal control scheme, this reaction exceeded the boiling point of one of the reactants. A central composite experiment design explored the effects of reactant net flow rate, oscillation intensity and cooling capacity on the thermal and chemical response of the reaction. The HPOBR was able to passively control the temperature below the boiling point of the reactant at all conditions through heat spreading. Overall, a combined 260-fold improvement in throughput was demonstrated compared to a reactor requiring the use of a solvent. Thus, this ii wholly new reactor design provides a new approach to achieving green chemistry that could be theoretically easily adapted to other reactions. III. Analysis of in situ Fourier transform infrared (FTIR) spectroscopic data also suggested that the reaction kinetics of this solventless imination case study could be screened for the first time using the HPOBR and JOBR. This was tested by applying flow-screening protocols that adjusted the reactant molar ratio, residence time, and temperature in a single flow experiment. Both reactor configurations were able to screen the Arrhenius kinetics parameters (pre-exponential factors, activation energies, and equilibrium constants) of both steps of the imination reaction. By defining experiment conditions using design of experiments (DoE) methodologies, a theoretical 70+% reduction in material usage/time requirement for screening was achieved compared to the previous state-of-the-art screening using meso-OBRs in the literature. Additionally, it was discovered that thermal effects on the reaction could be inferred by changing other operating conditions such as molar ratio and residence time. This further simplifies the screening protocols by eliminating the need for active temperature control strategies (such as a jacket). IV. Finally, potential application areas for further development of the meso-OBR platform using 3D printing were devised. These areas conformed to different “hierarchies” of complexity, from new baffle structures (simplest) to entirely new methods for achieving mixing (most complex). This latter option was adopted as a case study, where the passively generated pulsatile flows of fluidic oscillators were tested for the first time as a means for improving plug flow. Improved plug flow behaviour was indeed demonstrated in three different standard reactor geometries (plain, baffled and coiled tubes), where it could be inferred that axial dispersion was decoupled from the secondary flows in an analogous manner to the OBR. The results indicate that these devices could be the basis for a new flow chemistry platform that requires no moving parts, which would be appealing for various industrial applications. It is concluded that, for the meso-OBR platform to remain relevant in the next era of tailor-made reactors (with rapid uptake of 3D printing), the identified areas where 3D printing could benefit the meso-OBR should be further explored