Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Nonlinear identification of power electronic systems

This paper presents a new approach to modelling power electronic systems using nonlinear system identification. By employing the nonlinear autoregressive moving average with exogenous input (NARMAX) technique, the parametric model of power electronic systems can be derived from the time-domain data. This approach possesses some advantages over available circuit-oriented modelling approaches, such as no small-signal approximation, no circuit idealization and no detailed knowledge of system operation. Moreover, it is found that the inclusion of nonlinear terms in the model of power electronic systems is particularly necessary during the presence of large-signal perturbation.published_or_final_versio

Reduced-order modeling of power electronics components and systems

This dissertation addresses the seemingly inevitable compromise between modeling fidelity and simulation speed in power electronics. Higher-order effects are considered at the component and system levels. Order-reduction techniques are applied to provide insight into accurate, computationally efficient component-level (via reduced-order physics-based model) and system-level simulations (via multiresolution simulation). Proposed high-order models, verified with hardware measurements, are, in turn, used to verify the accuracy of final reduced-order models for both small- and large-signal excitations. At the component level, dynamic high-fidelity magnetic equivalent circuits are introduced for laminated and solid magnetic cores. Automated linear and nonlinear order-reduction techniques are introduced for linear magnetic systems, saturated systems, systems with relative motion, and multiple-winding systems, to extract the desired essential system dynamics. Finite-element models of magnetic components incorporating relative motion are set forth and then reduced. At the system level, a framework for multiresolution simulation of switching converters is developed. Multiresolution simulation provides an alternative method to analyze power converters by providing an appropriate amount of detail based on the time scale and phenomenon being considered. A detailed full-order converter model is built based upon high-order component models and accurate switching transitions. Efficient order-reduction techniques are used to extract several lower-order models for the desired resolution of the simulation. This simulation framework is extended to higher-order converters, converters with nonlinear elements, and closed-loop systems. The resulting rapid-to-integrate component models and flexible simulation frameworks could form the computational core of future virtual prototyping design and analysis environments for energy processing units

Analysis And Design Optimization Of Multiphase Converter

Future microprocessors pose many challenges to the power conversion techniques. Multiphase synchronous buck converters have been widely used in high current low voltage microprocessor application. Design optimization needs to be carefully carried out with pushing the envelope specification and ever increasing concentration towards power saving features. In this work, attention has been focused on dynamic aspects of multiphase synchronous buck design. The power related issues and optimizations have been comprehensively investigated in this paper. In the first chapter, multiphase DC-DC conversion is presented with background application. Adaptive voltage positioning and various nonlinear control schemes are evaluated. Design optimization are presented to achieve best static efficiency over the entire load range. Power loss analysis from various operation modes and driver IC definition are studied thoroughly to better understand the loss terms and minimize the power loss. Load adaptive control is then proposed together with parametric optimization to achieve optimum efficiency figure. New nonlinear control schemes are proposed to improve the transient response, i.e. load engage and load release responses, of the multiphase VR in low frequency repetitive transient. Drop phase optimization and PWM transition from long tri-state phase are presented to improve the smoothness and robustness of the VR in mode transition. During high frequency repetitive transient, the control loop should be optimized and nonlinear loop should be turned off. Dynamic current sharing are thoroughly studied in chapter 4. The output impedance of the multiphase v synchronous buck are derived to assist the analysis. Beat frequency is studied and mitigated by proposing load frequency detection scheme by turning OFF the nonlinear loop and introducing current protection in the control loop. Dynamic voltage scaling (DVS) is now used in modern Multi-Core processor (MCP) and multiprocessor System-on-Chip (MPSoC) to reduce operational voltage under light load condition. With the aggressive motivation to boost dynamic power efficiency, the design specification of voltage transition (dv/dt) for the DVS is pushing the physical limitation of the multiphase converter design and the component stress as well. In this paper, the operation modes and modes transition during dynamic voltage transition are illustrated. Critical dead-times of driver IC design and system dynamics are first studied and then optimized. The excessive stress on the control MOSFET which increases the reliability concern is captured in boost mode operation. Feasible solutions are also proposed and verified by both simulation and experiment results. CdV/dt compensation for removing the AVP effect and novel nonlinear control scheme for smooth transition are proposed for dealing with fast voltage positioning. Optimum phase number control during dynamic voltage transition is also proposed and triggered by voltage identification (VID) delta to further reduce the dynamic loss. The proposed schemes are experimentally verified in a 200 W six phase synchronous buck converter. Finally, the work is concluded. The references are listed

DESIGN, COMPACT MODELING AND CHARACTERIZATION OF NANOSCALE DEVICES

Electronic device modeling is a crucial step in the advancement of modern nanotechnology and is gaining more and more interest. Nanoscale complementary metal oxide semiconductor (CMOS) transistors, being the backbone of the electronic industry, are pushed to below 10 nm dimensions using novel manufacturing techniques including extreme lithography. As their dimensions are pushed into such unprecedented limits, their behavior is still captured using models that are decades old. Among many other proposed nanoscale devices, silicon vacuum electron devices are regaining attention due to their presumed advantages in operating at very high power, high speed and under harsh environment, where CMOS cannot compete. Another type of devices that have the potential to complement CMOS transistors are nano-electromechanical systems (NEMS), with potential applications in filters, stable frequency sources, non-volatile memories and reconfigurable and neuromorphic electronics

Modeling and Loss Analysis of SiC Power Semiconductor Devices for Switching Converter Applications

Since its inception, power electronics has been to a large extent driven by the available power semiconductor devices. Switching power converter topologies, modes of operation, switching frequencies, passive filtering elements are chosen based on the switching and conduction characteristics of power semiconductor devices. In recent times new wide bandgap power semiconductor devices, such as SiC MOSFETs, are emerging with superior performance as compared to conventional silicon devices. In switching power converter design, power losses of the power semiconductor de- vices play a crucial role in determining the physical characteristics of power converter systems in terms of size, weight, efficiency and, ultimately, cost. Switching losses impose an upper limit to the switching frequency, which in turn determines passive filtering element sizes and dimensioning of the cooling system. An accurate power loss model of the power semiconductor devices is needed for switching power con- verter design and optimization and to quantify the system-level advantages of novel SiC devices compared to conventional silicon devices. Since power semiconductor device performance plays a key role in power electron- ics applications, power electronics designers need circuit-oriented device models to simulate the in-circuit performance of power devices in different applications. The basic objective in device modeling is to obtain a predictive description of the current flow through the device as a function of the applied voltages and currents, environ- mental conditions, such as temperature and radiation, and physical characteristics, such as geometry, doping levels, and so on. In general, there is a trade-off between computational speed and model accuracy. The required accuracy and simulation timeare crucial factors considered by device model designers when making this tradeoff. In this dissertation, the analysis and applications of wide bandgap power devices can be divided into two parts: development of analytical loss model for wide bandgap power devices, and development of wide bandgap power semiconductor device models. In the first part, a simple and accurate analytical switching loss model for SiC power devices is developed. This model considers the device capacitances and the parasitic inductances in the circuit, which have a strong impact on switching losses. In addition, the reverse recovery effect of the body diode of SiC MOSFET is considered. The detailed analysis of turn-on and turn-off transitions is presented. The accuracy of the proposed model is validated by experimental results, and the accuracy of the proposed loss model and conventional piecewise linear loss model is compared. The proposed analytical loss model has several advantages: it gives insight into the switching process, showing how different parameters and parasitics affect switching waveforms and determine switching losses; it provides accurate and simple closed-form switching loss calculation; it is useful for optimization given the fast calculation speed and the absence of numerical convergence problems; all power device parameters can be derived from datasheets (but requires parasitics estimation); it includes MOSFET body diode reverse recovery; it provides piecewise linear estimate of actual switching waveforms. In the second part, a simple and accurate circuit-simulator compact model for sili- con carbide (SiC) MOSFET is proposed and validated under both static and switching conditions. A novel feature of the proposed model is that it takes into account the nonlinear parasitic capacitances of the device and parameter extraction requires only data from device manufacturer datasheet. A parameter extraction procedure is pro- posed. A simulation model is built in Pspice software tool. The PSpice simulation results are compared with datasheet results. The comparison shows good agreement between simulation and datasheet results for both static and dynamic characteris-tics

Accurate modeling techniques for power delivery

“Power delivery is essential in electronic systems to provide reliable power from voltage sources to load devices. Driven by the ambitious user demands and technology evolutions, the power delivery design is posed serious challenges. In this work, we focus on modeling two types of power delivery paths: the power distribution network (PDN) and the wireless power transfer (WPT) system. For the modeling of PDN, a novel pattern-based analytical method is proposed for PCB-level PDN impedance calculations, which constructs an equivalent circuit with one-to-one correspondences to the PCB’s physical structure. A practical modeling methodology is also introduced to optimize the PDN design. In addition, a topology-based behavior model is developed for the current-mode voltage regulator module (VRM). This model includes all the critical components in the power stage, the voltage control loop, and the current control loop of a VRM device. A novel method is also proposed to unify the modeling of the continuous and discontinuous conduction modes for transient load responses. Cascading the proposed VRM model with the PCB-level PDN model enables a combined PDN analysis, which is much needed for modern PDN designs. For the modeling of WPT system, a system-level model is developed for both efficiency and power loss of all the blocks in WPT systems. A rectifier characterization method is also proposed to obtain the accurate load impedance. This model is capable of deriving the power capabilities for both the fundamental and higher order harmonics. Based on the system model, a practical design methodology is introduced to simultaneously optimize multiple system parameters, which greatly accelerates the design process”--Abstract, page iv

Modeling and Simulation in Engineering

The general aim of this book is to present selected chapters of the following types: chapters with more focus on modeling with some necessary simulation details and chapters with less focus on modeling but with more simulation details. This book contains eleven chapters divided into two sections: Modeling in Continuum Mechanics and Modeling in Electronics and Engineering. We hope our book entitled "Modeling and Simulation in Engineering - Selected Problems" will serve as a useful reference to students, scientists, and engineers