Skyrmion Hall Effect Revealed by Direct Time-Resolved X-Ray Microscopy

Magnetic skyrmions are highly promising candidates for future spintronic applications such as skyrmion racetrack memories and logic devices. They exhibit exotic and complex dynamics governed by topology and are less influenced by defects, such as edge roughness, than conventionally used domain walls. In particular, their finite topological charge leads to a predicted "skyrmion Hall effect", in which current-driven skyrmions acquire a transverse velocity component analogous to charged particles in the conventional Hall effect. Here, we present nanoscale pump-probe imaging that for the first time reveals the real-time dynamics of skyrmions driven by current-induced spin orbit torque (SOT). We find that skyrmions move at a well-defined angle {\Theta}_{SH} that can exceed 30{\deg} with respect to the current flow, but in contrast to theoretical expectations, {\Theta}_{SH} increases linearly with velocity up to at least 100 m/s. We explain our observation based on internal mode excitations in combination with a field-like SOT, showing that one must go beyond the usual rigid skyrmion description to unravel the dynamics.Comment: pdf document arxiv_v1.1. 24 pages (incl. 9 figures and supplementary information

Shiftsreduce: Minimizing shifts in racetrack memory 4.0

Racetrack memories (RMs) have significantly evolved since their conception in 2008, making them a serious contender in the field of emerging memory technologies. Despite key technological advancements, the access latency and energy consumption of an RM-based system are still highly influenced by the number of shift operations. These operations are required to move bits to the right positions in the racetracks. This article presents data-placement techniques for RMs that maximize the likelihood that consecutive references access nearby memory locations at runtime, thereby minimizing the number of shifts. We present an integer linear programming (ILP) formulation for optimal data placement in RMs, and we revisit existing offset assignment heuristics, originally proposed for random-access memories. We introduce a novel heuristic tailored to a realistic RM and combine it with a genetic search to further improve the solution. We show a reduction in the number of shifts of up to 52.5%, outperforming the state of the art by up to 16.1%

A taxonomy of parallel sorting

TR 84-601In this paper, we propose a taxonomy of parallel sorting that includes a broad range of array and file sorting algorithms. We analyze the evolution of research on parallel sorting, from the earliest sorting networks to the shared memory algorithms and the VLSI sorters. In the context of sorting networks, we describe two fundamental parallel merging schemes - the odd-even and the bitonic merge. Sorting algorithms have been derived from these merging algorithms for parallel computers where processors communicate through interconnection networks such as the perfect shuffle, the mesh and a number of other sparse networks. After describing the network sorting algorithms, we show that, with a shared memory model of parallel computation, faster algorithms have been derived from parallel enumeration sorting schemes, where keys are first ranked and then rearranged according to their rank

Data systems elements technology assessment and system specifications, issue no. 1

The ability to satisfy the objectives of future NASA Office of Applications Programs is dependent on technology advances in a number of areas of data systems. The technology of end-to-end data systems (space generator elements through ground processing, dissemination, and presentation, is examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development

The artificial retina processor for track reconstruction at the LHC crossing rate

We present results of an R&D study for a specialized processor capable of precisely reconstructing, in pixel detectors, hundreds of charged-particle tracks from high-energy collisions at 40 MHz rate. We apply a highly parallel pattern-recognition algorithm, inspired by studies of the processing of visual images by the brain as it happens in nature, and describe in detail an efficient hardware implementation in high-speed, high-bandwidth FPGA devices. This is the first detailed demonstration of reconstruction of offline-quality tracks at 40 MHz and makes the device suitable for processing Large Hadron Collider events at the full crossing frequency.Comment: 4th draft of WIT proceedings modified according to JINST referee's comments. 10 pages, 6 figures, 2 table

Data systems elements technology assessment and system specifications, issue no. 2

The ability to satisfy the objectives of future NASA Office of Applications programs is dependent on technology advances in a number of areas of data systems. The hardware and software technology of end-to-end systems (data processing elements through ground processing, dissemination, and presentation) are examined in terms of state of the art, trends, and projected developments in the 1980 to 1985 timeframe. Capability is considered in terms of elements that are either commercially available or that can be implemented from commercially available components with minimal development

Space station data system analysis/architecture study. Task 2: Options development DR-5. Volume 1: Technology options

The second task in the Space Station Data System (SSDS) Analysis/Architecture Study is the development of an information base that will support the conduct of trade studies and provide sufficient data to make key design/programmatic decisions. This volume identifies the preferred options in the technology category and characterizes these options with respect to performance attributes, constraints, cost, and risk. The technology category includes advanced materials, processes, and techniques that can be used to enhance the implementation of SSDS design structures. The specific areas discussed are mass storage, including space and round on-line storage and off-line storage; man/machine interface; data processing hardware, including flight computers and advanced/fault tolerant computer architectures; and software, including data compression algorithms, on-board high level languages, and software tools. Also discussed are artificial intelligence applications and hard-wire communications

FBI fingerprint identification automation study. AIDS 3 evaluation report. Volume 2: Technical feasibility

The results of this effort are presented in a manner for use by both the AIDS 3 Operational and Economic Feasibility subtasks as well as the Development of Alternative subtask. The approach taken was to identify the major functions that appear in AIDS 3 and then to determine which technologies would be needed for support. The technologies were then examined from the point of view of reliability, throughput, security, availability, cost and possible future trends. Whenever possible graphs are given to indicate projected costs of rapidly changing technologies

Memory technology survey

The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed