Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction

Voltage sensing based built-in current sensor for IDDQ test

Quiescent current leakage test of the VDD supply (IDDQ Test) has been proven an effective way to screen out defective chips in manufacturing of Integrated Circuits (IC). As technology advances, the traditional IDDQ test is facing more and more challenges. In this research, a practical built-in current sensor (BICS) is proposed and the design is verified by three generations of test chips. The BICS detects the signal by sensing the voltage drop on supply lines of the circuit under test (CUT). Then the sensor performs analog-to-digital conversion of the input signal using a stochastic process with scan chain readout. Self-calibration and digital chopping are used to minimize offset and low frequency noise and drift. This non-invasive procedure avoids any performance degradation of the CUT. The measurement results of test chips are presented. The sensor achieves a high IDDQ resolution with small chip area overhead. This will enable IDDQ of future technology generations

On the deployment of on-chip noise sensors

The relentless technology scaling has led to significantly reduced noise margin and complicated functionalities. As such, design time techniques per se are less likely to ensure power integrity, resulting in runtime voltage emergencies. To alleviate the issue, recently several works have shed light on the possibilities of dynamic noise management systems. Most of these works rely on on-chip noise sensors to accurately capture voltage emergencies. However, they all assume that the placement of the sensors is given. It remains an open problem in the literature how to optimally place a given number of noise sensors for best voltage emergency detection. The problem of noise sensor placement is defined at first along with a novel sensing quality metric (SQM) to be maximized. The threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. The problem of minimizing the system alarm rate subject to a given system failure rate constraint is formulated. It is further shown that with the help of IDDQ measurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. In the third chapter, a novel framework to predict the resonance frequency using existing on-chip noise sensors, based on the theory of 1-bit compressed sensing is proposed. The proposed framework can help to achieve the resonance frequency of individual chips so as to effectively avoid resonance noise at runtime --Abstract, page iii

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Dependable reconfigurable multi-sensor poles for security

Wireless sensor network poles for security monitoring under harsh environments require a very high dependability as they are safety-critical [1]. An example of a multi-sensor pole is shown. Crucial attribute in these systems for security, especially in harsh environment, is a high robustness and guaranteed availability during lifetime. This environment could include molest. In this paper, two approaches are used which are applied simultaneously but are developed in different projects. \u

Memory Module Design for High-Temperature Applications in SiC CMOS Technology

The wide bandgap (WBG) characteristics of SiC play a significant and disruptive role in the power electronics industry. The same characteristics make this material a viable choice for high-temperature electronics systems. Leveraging the high-temperature capability of SiC is crucial to automotive, space exploration, aerospace, deep well drilling, and gas turbines. A significant issue with the high-temperature operation is the exponential increase in leakage current. The lower intrinsic carrier concentration of SiC (10-9 cm-3) compared to Si (1010 cm-3) leads to lower leakage over temperature. Several researchers have demonstrated analog and digital circuits designed in SiC. However, a memory module is required to realize a complete electronic system in SiC that bridges the gap between data processing and data storage. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for future electronics. A novel static random-access memory (SRAM) cell is designed and implemented in a SiC 1 µm triple well CMOS process for high-temperature applications in this work. The prevalent issues encountered during SiC fabrication and the uncertainties in device performance led to 6T SRAM cell design modifications that enable adaptability to the worst and the best cases. However, design trade-offs are made in the design size, the number of transistors, number of I/Os, and the cell\u27s power consumption. The novel SRAM cell design mitigates the effect of poor p-type contacts after the device fabrication by controlling the cell\u27s drive strength via an additional pull-up network. The design also includes two parallel access transistors and separate wordlines that control both access transistors. This individual control enables post-fabrication tunability in the cell ratio (CR) and the pull-up (PR) ratio of the cell. It also allows tuning the access transistors\u27 effective width during a data read operation, and a data write operation, independently. Along with the SRAM cell design, the conventional latch-based sense amplifier is also designed in the SiC CMOS process to realize the monolithic memory IC modules. The SRAM cell performance is evaluated on the basis of static noise margin (SNM), write SNM (WSNM), read SNM (RSNM), leakage current, and read access time over a wide temperature range (25ºC to 500ºC) on three uniquely processed wafers. The noise margins measured on Wafer #2 show a lower leakage current of ~500 nA at 500ºC with the supply voltage of 10 V. The SNM of 6.07 V is measured at 500ºC with a 10 V of power supply. The read access time at 400ºC is ~7.5 µs at a supply voltage of 10 V

Development of Test Procedure For CMOS Operational Amplifier Application Circuits

The integrated circuit (IC) is an ultra-small and fragile electrical system. A chip is basically an IC placed in a protective black plastic casing. The only contact the outside world has with the IC is through the chips input-output and power supply pins. ICs are also prone to damage and to locate damages inside a chip requires special probing techniques. These techniques are incorporated from the beginning of the design stage of a chip. Design for Testability (DFT) is a method applied to the design stage of chips such that electrical testing of the chips at the end of the production stage is greatly simplified. For a chip manufacturer, DFT helps cut production cost by shortening the time to test finished chips w hich eventually decreases the time to market the chip. Built-In Self Test (BIST) chips, an outcome of DFT, are ICs designed with extended circuitry dedicated to test its electrical behavior which eventually could inform a manufacturer w here damage has occurred. The testing circuitry inside a BIST chip is complimented by a test pattern, which is a special signal that executes the actual testing. The main objective of this study is to develop a test procedure to test CMOS Operational Amplifier (Op-Amp) application circuits. The focus in the development of the testing procedure is to find a suitable test pattern. The study conducted results in the success of developing the said test procedure. The development of the test procedure is aided by a powerful computer software from Tanner Research Inc. called Tanner Tools. It is used for circuit simulation and development of a mask layout for an Op-Amp. The major findings of this thesis is that a faulty Op-Amp application circuit behaves differently from a faultless Op-Amp application circuit. From this finding a test pattern can be derived by comparing between faulty and faultless Op-Amp application circuit behavior through simulation. The only disadvantage of the test pattern is that it could only detect damages in the Op-Amp if the damages occurs only one at any given time. Thus it can be argued that in relation to DFT for an Op-Amp application circuit, it is not impossible for damages to be pin-pointed using the developed procedure

Nano-Power Integrated Circuits for Energy Harvesting

The energy harvesting research field has grown considerably in the last decade due to increasing interests in energy autonomous sensing systems, which require smart and efficient interfaces for extracting power from energy source and power management (PM) circuits. This thesis investigates the design trade-offs for minimizing the intrinsic power of PM circuits, in order to allow operation with very weak energy sources. For validation purposes, three different integrated power converter and PM circuits for energy harvesting applications are presented. They have been designed for nano-power operations and single-source converters can operate with input power lower than 1 μW. The first IC is a buck-boost converter for piezoelectric transducers (PZ) implementing Synchronous Electrical Charge Extraction (SECE), a non-linear energy extraction technique. Moreover, Residual Charge Inversion technique is exploited for extracting energy from PZ with weak and irregular excitations (i.e. lower voltage), and the implemented PM policy, named Two-Way Energy Storage, considerably reduces the start-up time of the converter, improving the overall conversion efficiency. The second proposed IC is a general-purpose buck-boost converter for low-voltage DC energy sources, up to 2.5 V. An ultra-low-power MPPT circuit has been designed in order to track variations of source power. Furthermore, a capacitive boost circuit has been included, allowing the converter start-up from a source voltage VDC0 = 223 mV. A nano-power programmable linear regulator is also included in order to provide a stable voltage to the load. The third IC implements an heterogeneous multisource buck-boost converter. It provides up to 9 independent input channels, of which 5 are specific for PZ (with SECE) and 4 for DC energy sources with MPPT. The inductor is shared among channels and an arbiter, designed with asynchronous logic to reduce the energy consumption, avoids simultaneous access to the buck-boost core, with a dynamic schedule based on source priority

Investigation of Current Sensing Using Inherent Resistance

A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named “IRS” here, and it stands for Inherent Resistance Current Sensing. To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area. It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor. In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them. Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided