Process development and reliability of thin gate oxides

The Semiconductor Industry Association\u27s (SIA) current National Technological Roadmap calls for the development of a suitable dielectric material for use in gate oxide for the 0.18|micrometers generation of chips and beyond. Some of the key challenges identified are resistance to oxide trapped charge generation from higher levels of tunneling currents and/or plasma processing, and formation of an effective barrier to dopant penetration during the gate processing. One promising material to meet these challenges is nitrided thermal oxide. Development of a growth process that yields high quality, lOnm thick, thermally grown Si02 films at RJT for use as a gate dielectric is described. Thin oxides (8nm - 20nm) were grown by thermal oxidation followed by inert anneals in Ar and N2. Nitrided oxides were created by implanting N2 (dose range: 5el3 - lei 5 /cm2) into the substrate prior to gate oxidation. Test equipment was setup to study Fowler Nordheim (FN) tunneling and dielectric breakdown. Test structures consisted of conventional and novel MOS capacitor structures with aluminum and poly-silicon gate electrodes. Scaling RJT\u27s existing, 20nm oxidation process to lOnm resulted in degradation of dielectric strength from \u3e lOMV/cm to ~6-7MV/cm for Al-gate MOS capacitors. Replacing the Al gate material with poly-silicon restored the dielectric strength to lOMV/cm. Performing an N2 implant through a screening oxide, prior to gate oxidation, was investigated as a means of obtaining a nitrided thermal oxide. For certain doses (5el3 - 5el4 /cm2), Al-gate MOS capacitors exhibited an improved dielectric strength as the mean value increased from 6- 7MV/cm to ~9MV/cm. Poly-Si gate MOS capacitors showed a similar improvement for the nitrided oxides, exhibiting mean dielectric strength values in the 10-12MV/cm range. Fowler- Nordheim (FN) tunnel current measurements showed that the nitrided films exhibit lower leakage levels and less charge trapping than their thermal Si02 counterparts. Results indicate that a 12nm nitrided oxide, for a certain dose (5el4/cm2), exhibited equivalent electrical performance to a 20nm thermally grown Si02 oxide. In conclusion, a process was developed for yielding reliable thin gate oxides (~10nm) in a university fab

Investigation of induced charge damage on self-aligned metal-gate MOS devices

MOS capacitors and NMOS transistors were fabricated with various gate oxides and inter- level dielectrics (ILDs) in order to study the effects of plasma induced charging during the post-metal plasma deposition of an insulating oxide layer. The gate oxides investigated include thermal SiO 2, a low temperature oxide (LTO) deposited by low pressure chemical vapor deposition (LPCVD) using silane and oxygen, and an oxide deposited by plasma enhanced chemical vapor deposition (PECVD) using tetra-ethylortho- silicate (TEOS) as a precursor. A standard-recipe TEOS-based ILD was studied, as well as an alternative recipe that utilized decreased power. Additional wafers were fabricated with an LTO ILD to serve as a control group in order to isolate the influence of the ILD deposition on the respective gate dielectric. By studying C-V and I-V characteristics, both interfacial degradation as well as bulk charging was demonstrated as a result of the PECVD ILD deposition. The investigation demonstrated clear differences in plasma- induced charge effects on the various gate dielectrics. A correlation between the ILD deposition power and the resulting charge influence was established. In addition, post-plasma annealing experiments were done to study the thermal stability of induced charge

Nanoscale characterisation of dielectrics for advanced materials and electronic devices

PhD ThesisStrained silicon (Si) and silicon-germanium (SiGe) devices have long been recognised for their enhanced mobility and higher on-state current compared with bulk-Si transistors. However, the performance and reliability of dielectrics on strained Si/strained SiGe is usually not same as for bulk-Si. Epitaxial growth of strained Si/SiGe can induce surface roughness. The typical scale of surface roughness is generally higher than bulk-Si and can exceed the device size. Surface roughness has previously been shown to impact the electrical properties of the gate dielectric. Conventional macroscopic characterisation techniques are not capable of studying localised electrical behaviour, and thus prevent an understanding of the influence of large scale surface roughness. However scanning probe microscopy (SPM) techniques are capable of simultaneously imaging material and electrical properties. This thesis focuses on understanding the relationship between substrate induced surface roughness and the electrical performance of the overlying dielectric in high mobility strained Si/SiGe devices. SPM techniques including conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been applied to tensile strained Si and compressively strained SiGe materials and devices, suitable for enhancing electron and hole mobility, respectively. Gate leakage current, interface trap density, breakdown behaviour and dielectric thickness uniformity have been studied at the nanoscale. Data obtained by SPM has been compared with macroscopic electrical data from the same devices and found to be in good agreement. For strained Si devices exhibiting the typical crosshatch morphology, the electrical performance and reliability of the dielectric is strongly influenced by the roughness. Troughs and slopes of the crosshatch morphology lead to degraded gate leakage and trapped charge at the interface compared with peaks on the crosshatch undulations. Tensile strained Si material which does not exhibit the crosshatch undulation exhibits improved uniformity in dielectric properties. Quantitative agreement has been found for leakage at a device-level and nanoscale, when accounting for the tip area. The techniques developed can be used to study individual defects or regions on dielectrics whether grown or deposited (including high-κ) and on different substrates including strained Si on insulator (SSOI), strained Ge on insulator (SGOI), strained Ge, silicon carbide (SiC) and graphene. Strained SiGe samples with Ge content varying from 0 to 65% have also been studied. The increase in leakage and trapped charge density with increasing Ge extracted from SPM data is in good agreement with theory and macroscopic data. The techniques appear to be very sensitive, with SCM analysis detecting other dielectric related defects on a 20% Ge sample and the effects of the 65% Ge later exceeding the critical thickness (increased defects and variability in characteristics). Further applications and work to advance the use of electrical SPM techniques are also discussed. These include anti-reflective coatings, synthetic chrysotile nanotubes and sensitivity studies.Overseas Research Students Awards Scheme (ORSAS), School International Research Scholarship (SIRS), Newcastle University International Postgraduate Scholarship (NUIPS) and the Strained Si/SiGe platform grant

Characterization of materials and fabrication of active matrix thin film transistor arrays for electrical interfacing of biological materials

Electrical interfacing between semiconductor devices and biological materials has been studied for live cell probing which will make it possible to perform direct electrical sensing of cells. To extend the applicability of extracellular and planar microelectrode arrays, recently vertically aligned nanofibers (VACNFs) have been integrated with micro electrode arrays (MEA) for applications such as cell membrane mimics, gene delivery arrays, neuroelectrochemical interfacing arrays, superhydrophobic switches, and intracellular probes. The main drawback of VACNF-MEA devices are the low density of electrodes and passive addressing approach. In order to increase the number of elements of an MEA and enable both stimulation and recording on the same platform, an actively addressed thin film transistor (TFT) array platform was developed. Active matrix-TFTs are highly functional devices which have been used widely as backplanes in display electronics field over the past few decades.VACNFs were integrated onto the TFT array (TFT-VACNF) as they enhance the electrical sensitivity to the cell relative to standard planar arrays; furthermore, the vertical electrodes provide the potential for intracellular sensing within individual cells. This device platform provides great potential as an advanced microelectrode array for direct cell sensing, probing, and recording with a high electrode density and active addressability. In this study, VACNFs were successfully integrated onto TFT devices to demonstrate a new microelectrode array platform. The materials and processes of the TFT structure were designed to be compatible with the requisite high-temperature (~700°C) and direct current Plasma Enhanced Chemical Vapor Deposition (dc-PECVD) VACNF growth process.To extend the applicability of utilizing these vertical electrodes, this dissertation describes: the characterization and optimization of each layer for the TFT; the fabrication process and issues for active matrix TFT array; the critical device integration issues of VACNFs onto active matrix TFT arrays are elaborated; and the initial and final device characteristics are reported

Silicon Nitride Deposition, Chromium Corrosion Mechanisms and Source/Drain Parasitic Resistance in Amorphous Silicon Thin Film transistors

Hydrogenated amorphous silicon (a-Si:H) based thin film transistors (TFTs) are finding increased application as switching elements in active-matrix liquid crystal displays (AMLCDs). Extensive research has been focussed on optimizing fabrication conditions to improve materials quality and on reducing channel length to increase device speed. However, the basic physics and chemistry have not yet been fully understood. In addition, little attention has been paid to the significant effect of source/drain parasitics. The work described in this thesis is closely related to the speed and stability issues on the discrete device level. Specifically, the influence of gate nitride deposition and its NH3 plasma treatment has been studied. The competing effects of nitridation reaction and radiation damage were found to cause an interesting trade-off between the device stability and speed. Further effort was devoted to the analysis of an important TFT failure phenomenon. Both electrical and spectroscopic techniques were utilized for gate Cr corrosion studies. It was determined that the corrosion was largely promoted by the CF4 plasma exposure of Cr during the fabrication. Finally, new test structures were designed, fabricated and characterized to study the source/drain parasitic resistance

Oxygen-insertion Technology for CMOS Performance Enhancement

Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance ($R_{sh}$) with decreasing junction depth ($X_J$) for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of $R_{sh}$ test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing $R_{sh}$ and $X_J$ due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase $R_{sh}$ unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher $I_{on}/I_{off}$ ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low $V_{DD,min}$ for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in $V_{DD,min}$ compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height ($\Phi_{Bp}$) of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in $\Phi_{Bp}$ is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low-$\Phi_{Bp}$ Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate

HfO2 as gate dielectric on Si and Ge substrate

Hafnium oxide HfO2 has been considered as an alternative to silicon dioxide SiO2 in future nano-scale complementary metal-oxide-semiconductor (CMOS) devices since it provides the required capacitance at the reduced device size because of its high dielectric constant. HfO2 films are currently deposited by various techniques. Many of them require high temperature annealing that can impact device performance and reliability. In this research, electrical characteristics of capacitors with HfO2 as gate dielectric deposited by standard thermal evaporation and e-beam evaporation on Si and Ge substrates were investigated. The dielectric constant of HfO2 deposited by thermal evaporation on Si is in the range of 18-25. Al/HfO2/Si MOS capacitors annealed at 450°C show low hysteresis, leakage current density and bulk oxide charges. Interface state density and low temperature charge trapping behavior of these structures were also investigated. Degradation in surface carrier mobility has been reported in Si field-effect-transistors with HfO2 as gate dielectric. To explore the possibility of alleviating this problem we have used germanium (Ge) substrate as this semiconductor has higher carrier mobility than Si. Devices fabricated by depositing HfO2 directly on Ge by standard thermal evaporation were found to be too leaky and show significant hysteresis and large shift in flatband voltage. This deterioration in electrical performance is mainly due to the formation of unstable interfacial layer of GeO2 during the HfO2 deposition. To minimize this effect, Ge surface was treated with the beam of atomic nitrogen prior to the dielectric deposition. The effect of surface nitridation, on interface as well as on bulk oxide, trap energy levels were investigated using low temperature C-V measurements. They revealed additional defect levels in the nitrided devices indicating diffusion of nitrogen from interface into the bulk oxide. Impact of surface nitridation on the reliability of Ge/HfO2/Al MOS capacitors has been investigated by application of constant voltage stress at different voltage levels for various time periods. It was observed that deeper trap levels in nitrided devices, found from low frequency and low temperature measurements, trap the charge carrier immediately after stress but with time these carriers detrap and create more traps inside the bulk oxide resulting in further devices deterioration. It is inferred that though nitrogen is effective in reducing interfacial layer growth it incorporates more defects at interface as well as in bulk oxide. Therefore, it is important to look into alternative methods of surface passivation to limit the growth of GeO2 at the interface

Advanced gate stack for sub-0.1 (mu)m CMOS technology

Ph.DDOCTOR OF PHILOSOPH