126 research outputs found
6T-SRAM 1Mb Design with Test Structures and Post Silicon Validation
abstract: Static random-access memories (SRAM) are integral part of design systems as caches and data memories that and occupy one-third of design space. The work presents an embedded low power SRAM on a triple well process that allows body-biasing control. In addition to the normal mode operation, the design is embedded with Physical Unclonable Function (PUF) [Suh07] and Sense Amplifier Test (SA Test) mode. With PUF mode structures, the fabrication and environmental mismatches in bit cells are used to generate unique identification bits. These bits are fixed and known as preferred state of an SRAM bit cell. The direct access test structure is a measurement unit for offset voltage analysis of sense amplifiers. These designs are manufactured using a foundry bulk CMOS 55 nm low-power (LP) process. The details about SRAM bit-cell and peripheral circuit design is discussed in detail, for certain cases the circuit simulation analysis is performed with random variations embedded in SPICE models. Further, post-silicon testing results are discussed for normal operation of SRAMs and the special test modes. The silicon and circuit simulation results for various tests are presented.Dissertation/ThesisMasters Thesis Electrical Engineering 201
Solid State Circuits Technologies
The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book
Contributions on using embedded memory circuits as physically unclonable functions considering reliability issues
[eng] Moving towards Internet-of-Things (IoT) era, hardware security becomes a crucial
research topic, because of the growing demand of electronic products that are remotely
connected through networks. Novel hardware security primitives based on
manufacturing process variability are proposed to enhance the security of the IoT
systems. As a trusted root that provides physical randomness, a physically unclonable
function is an essential base for hardware security.
SRAM devices are becoming one of the most promising alternatives for the
implementation of embedded physical unclonable functions as the start-up value of
each bit-cell depends largely on the variability related with the manufacturing process.
Not all bit-cells experience the same degree of variability, so it is possible that some cells
randomly modify their logical starting value, while others will start-up always at the
same value. However, physically unclonable function applications, such as identification
and key generation, require more constant logical starting value to assure high reliability
in PUF response. For this reason, some kind of post-processing is needed to correct the
errors in the PUF response.
Unfortunately, those cells that have more constant logic output are difficult to be
detected in advance. This work characterizes by simulation the start-up value
reproducibility proposing several metrics suitable for reliability estimation during design
phases. The aim is to be able to predict by simulation the percentage of cells that will be
suitable to be used as PUF generators. We evaluate the metrics results and analyze the
start-up values reproducibility considering different external perturbation sources like several power supply ramp up times, previous internal values in the bit-cell, and
different temperature scenarios. The characterization metrics can be exploited to
estimate the number of suitable SRAM cells for use in PUF implementations that can be
expected from a specific SRAM design.[cat] En l’era de la Internet de les coses (IoT), garantir la seguretat del hardware ha
esdevingut un tema de recerca crucial, en especial a causa de la creixent demanda de
productes electrònics que es connecten remotament a través de xarxes. Per millorar la
seguretat dels sistemes IoT, s’han proposat noves solucions hardware basades en la
variabilitat dels processos de fabricació. Les funcions físicament inclonables (PUF)
constitueixen una font fiable d’aleatorietat física i són una base essencial per a la
seguretat hardware.
Les memòries SRAM s’estan convertint en una de les alternatives més prometedores per
a la implementació de funcions físicament inclonables encastades. Això és així ja que el
valor d’encesa de cada una de les cel·les que formen els bits de la memòria depèn en
gran mesura de la variabilitat pròpia del procés de fabricació. No tots els bits tenen el
mateix grau de variabilitat, així que algunes cel·les canvien el seu estat lògic d’encesa de
forma aleatòria entre enceses, mentre que d’altres sempre assoleixen el mateix valor
en totes les enceses. No obstant això, les funcions físicament inclonables, que s’utilitzen
per generar claus d’identificació, requereixen un valor lògic d’encesa constant per tal
d’assegurar una resposta fiable del PUF. Per aquest motiu, normalment es necessita
algun tipus de postprocessament per corregir els possibles errors presents en la resposta
del PUF. Malauradament, les cel·les que presenten una resposta més constant són
difícils de detectar a priori.
Aquest treball caracteritza per simulació la reproductibilitat del valor d’encesa de cel·les
SRAM, i proposa diverses mètriques per estimar la fiabilitat de les cel·les durant les fases de disseny de la memòria. L'objectiu és ser capaç de predir per simulació el percentatge
de cel·les que seran adequades per ser utilitzades com PUF. S’avaluen els resultats de
diverses mètriques i s’analitza la reproductibilitat dels valors d’encesa de les cel·les
considerant diverses fonts de pertorbacions externes, com diferents rampes de tensió
per a l’encesa, els valors interns emmagatzemats prèviament en les cel·les, i diferents
temperatures. Es proposa utilitzar aquestes mètriques per estimar el nombre de cel·les
SRAM adients per ser implementades com a PUF en un disseny d‘SRAM específic.[spa] En la era de la Internet de las cosas (IoT), garantizar la seguridad del hardware se ha
convertido en un tema de investigación crucial, en especial a causa de la creciente
demanda de productos electrónicos que se conectan remotamente a través de redes.
Para mejorar la seguridad de los sistemas IoT, se han propuesto nuevas soluciones
hardware basadas en la variabilidad de los procesos de fabricación. Las funciones
físicamente inclonables (PUF) constituyen una fuente fiable de aleatoriedad física y son
una base esencial para la seguridad hardware.
Las memorias SRAM se están convirtiendo en una de las alternativas más prometedoras
para la implementación de funciones físicamente inclonables empotradas. Esto es así,
puesto que el valor de encendido de cada una de las celdas que forman los bits de la
memoria depende en gran medida de la variabilidad propia del proceso de fabricación.
No todos los bits tienen el mismo grado de variabilidad. Así pues, algunas celdas cambian
su estado lógico de encendido de forma aleatoria entre encendidos, mientras que otras
siempre adquieren el mismo valor en todos los encendidos. Sin embargo, las funciones
físicamente inclonables, que se utilizan para generar claves de identificación, requieren
un valor lógico de encendido constante para asegurar una respuesta fiable del PUF. Por
este motivo, normalmente se necesita algún tipo de posprocesado para corregir los
posibles errores presentes en la respuesta del PUF. Desafortunadamente, las celdas que
presentan una respuesta más constante son difíciles de detectar a priori.
Este trabajo caracteriza por simulación la reproductibilidad del valor de encendido de
celdas SRAM, y propone varias métricas para estimar la fiabilidad de las celdas durante las fases de diseño de la memoria. El objetivo es ser capaz de predecir por simulación el
porcentaje de celdas que serán adecuadas para ser utilizadas como PUF. Se evalúan los
resultados de varias métricas y se analiza la reproductibilidad de los valores de
encendido de las celdas considerando varias fuentes de perturbaciones externas, como
diferentes rampas de tensión para el encendido, los valores internos almacenados
previamente en las celdas, y diferentes temperaturas. Se propone utilizar estas métricas
para estimar el número de celdas SRAM adecuadas para ser implementadas como PUF
en un diseño de SRAM específico
Post-silicon Validation of Radiation Hardened Microprocessor and SRAM arrays
abstract: Digital systems are increasingly pervading in the everyday lives of humans. The security of these systems is a concern due to the sensitive data stored in them. The physically unclonable function (PUF) implemented on hardware provides a way to protect these systems. Static random-access memories (SRAMs) are designed and used as a strong PUF to generate random numbers unique to the manufactured integrated circuit (IC).
Digital systems are important to the technological improvements in space exploration. Space exploration requires radiation hardened microprocessors which minimize the functional disruptions in the presence of radiation. The design highly efficient radiation-hardened microprocessor for enabling spacecraft (HERMES) is a radiation-hardened microprocessor with performance comparable to the commercially available designs. These designs are manufactured using a foundry complementary metal-oxide semiconductor (CMOS) 55-nm triple-well process. This thesis presents the post silicon validation results of the HERMES and the PUF mode of SRAM across process corners.
Chapter 1 gives an overview of the blocks implemented on the test chip 25. It also talks about the pre-silicon functional verification methodology used for the test chip. Chapter 2 discusses about the post silicon testing setup of test chip 25 and the validation of the setup. Chapter 3 describes the architecture and the test bench of the HERMES along with its testing results. Chapter 4 discusses the test bench and the perl scripts used to test the SRAM along with its testing results. Chapter 5 gives a summary of the post-silicon validation results of the HERMES and the PUF mode of SRAM.Dissertation/ThesisMasters Thesis Electrical Engineering 201
Integrated Circuits/Microchips
With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications
Doctor of Philosophy
dissertationAdvancements in process technology and circuit techniques have enabled the creation of small chemical microsystems for use in a wide variety of biomedical and sensing applications. For applications requiring a small microsystem, many components can be integrated onto a single chip. This dissertation presents many low-power circuits, digital and analog, integrated onto a single chip called the Utah Microcontroller. To guide the design decisions for each of these components, two specific microsystems have been selected as target applications: a Smart Intravaginal Ring (S-IVR) and an NO releasing catheter. Both of these applications share the challenging requirements of integrating a large variety of low-power mixed-signal circuitry onto a single chip. These applications represent the requirements of a broad variety of small low-power sensing systems. In the course of the development of the Utah Microcontroller, several unique and significant contributions were made. A central component of the Utah Microcontroller is the WIMS Microprocessor, which incorporates a low-power feature called a scratchpad memory. For the first time, an analysis of scaling trends projected that scratchpad memories will continue to save power for the foreseeable future. This conclusion was bolstered by measured data from a fabricated microcontroller. In a 32 nm version of the WIMS Microprocessor, the scratchpad memory is projected to save ~10-30% of memory access energy depending upon the characteristics of the embedded program. Close examination of application requirements informed the design of an analog-to-digital converter, and a unique single-opamp buffered charge scaling DAC was developed to minimize power consumption. The opamp was designed to simultaneously meet the varied demands of many chip components to maximize circuit reuse. Each of these components are functional, have been integrated, fabricated, and tested. This dissertation successfully demonstrates that the needs of emerging small low-power microsystems can be met in advanced process nodes with the incorporation of low-power circuit techniques and design choices driven by application requirements
Design and Validation for FPGA Trust under Hardware Trojan Attacks
Field programmable gate arrays (FPGAs) are being increasingly used in a wide range of critical applications, including industrial, automotive, medical, and military systems. Since FPGA vendors are typically fabless, it is more economical to outsource device production to off-shore facilities. This introduces many opportunities for the insertion of malicious alterations of FPGA devices in the foundry, referred to as hardware Trojan attacks, that can cause logical and physical malfunctions during field operation. The vulnerability of these devices to hardware attacks raises serious security concerns regarding hardware and design assurance. In this paper, we present a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker. We also present an efficient Trojan detection method for FPGA based on a combined approach of logic-testing and side-channel analysis. Finally, we propose a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGA devices. We compare ATMR with the conventional TMR approach. The results demonstrate the advantages of ATMR over TMR with respect to power overhead, while maintaining the same or higher level of security and performances as TMR. Further improvement in overhead associated with ATMR is achieved by exploiting reconfiguration and time-sharing of resources
Energy-Efficient Neural Network Hardware Design and Circuit Techniques to Enhance Hardware Security
University of Minnesota Ph.D. dissertation. May 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); ix, 108 pages.Artificial intelligence (AI) algorithms and hardware are being developed at a rapid pace for emerging applications such as self-driving cars, speech/image/video recognition, deep learning, etc. Today’s AI tasks are mostly performed at remote datacenters, while in the future, more AI workloads are expected to run on edge devices. To fulfill this goal, innovative design techniques are needed to improve energy-efficiency, form factor, and as well as the security of AI chips. In this dissertation, two topics are focused on to address these challenges: building energy-efficient AI chips based on various neural network architectures, and designing “chip fingerprint” circuits as well as counterfeit chip sensors to improve hardware security. First of all, in order to deploy AI tasks on edge devices, we come up with various energy and area efficient computing platforms. One is a novel time-domain computing scheme for fully connected multi-layer perceptron (MLP) neural network and the other is an efficient binarized architecture for long short-term memory (LSTM) neural network. Secondly, to enhance the hardware security and ensure secure data communication between edge devices, we need to make sure the authenticity of the chip. Physical Unclonable Function (PUF) is a circuit primitive that can serve as a chip “fingerprint” by generating a unique ID for each chip. Another source of security concerns comes from the counterfeit ICs, and recycled and remarked ICs account for more than 80% of the counterfeit electronics. To effectively detect those counterfeit chips that have been physically compromised, we came up with a passive IC tamper sensor. This proposed sensor is demonstrated to be able to efficiently and reliably detect suspicious activities such as high temperature cycling, ambient humidity rise, and increased dust particles in the chip cavity
NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS
Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in
sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched
device pairs and mismatches, will cause circuit failure. This work is to assess the
NBTI effect considering the voltage and the temperature variations. It also provides a
working knowledge of NBTI awareness to the circuit design community for reliable
design of the SOC analog circuit. There have been numerous studies to date on the
NBTI effect to analog circuits. However, other researchers did not study the
implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The
reliability performance of all matched pair circuits, particularly the bandgap reference,
is at the mercy of aging differential. Reliability simulation is mandatory to obtain
realistic risk evaluation for circuit design reliability qualification. It is applicable to all
circuit aging problems covering both analog and digital. Failure rate varies as a
function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible
device and NBTI is the most vital failure mechanism for analog circuit in
sub-micrometer CMOS technology. This study provides a complete reliability
simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter
(DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In
order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in
experiment was conducted on the DAC circuits. The NBTI degradation observed in
the reliability simulation analysis has given a clue that under a severe stress condition,
a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in
experimental result on DAC proves the reliability sensitivity of NBTI to the DAC
circuitry
New Design Techniques for Dynamic Reconfigurable Architectures
L'abstract è presente nell'allegato / the abstract is in the attachmen
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