Unconstrained noninvasive vital signs monitoring for detection of obstructive sleep apnea with automated prevention

The Bioengineering Laboratory at UNH has demonstrated the usefulness of medical device interoperability through previous work that involved connecting an advanced hospital bed with blood pressure monitors over an electrical communication bus known as Controller Area Network (CAN). The medical devices utilize the software communication protocol known as CANopen for communicating relevant patient data to one another. This thesis explores the opportunity to detect a person\u27s heartbeat and respiration while lying in a hospital bed noninvasively and unconstrained for accurately identifying an episode of obstructive sleep apnea. The design and development of this device is a CANopen compatible therapeutic automatic bed adjustment to counteract a sleep apnea episode by restoring a person to normal respiratory sleep

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

Potential and Challenges of Analog Reconfigurable Computation in Modern and Future CMOS

In this work, the feasibility of the floating-gate technology in analog computing platforms in a scaled down general-purpose CMOS technology is considered. When the technology is scaled down the performance of analog circuits tends to get worse because the process parameters are optimized for digital transistors and the scaling involves the reduction of supply voltages. Generally, the challenge in analog circuit design is that all salient design metrics such as power, area, bandwidth and accuracy are interrelated. Furthermore, poor flexibility, i.e. lack of reconfigurability, the reuse of IP etc., can be considered the most severe weakness of analog hardware. On this account, digital calibration schemes are often required for improved performance or yield enhancement, whereas high flexibility/reconfigurability can not be easily achieved. Here, it is discussed whether it is possible to work around these obstacles by using floating-gate transistors (FGTs), and analyze problems associated with the practical implementation. FGT technology is attractive because it is electrically programmable and also features a charge-based built-in non-volatile memory. Apart from being ideal for canceling the circuit non-idealities due to process variations, the FGTs can also be used as computational or adaptive elements in analog circuits. The nominal gate oxide thickness in the deep sub-micron (DSM) processes is too thin to support robust charge retention and consequently the FGT becomes leaky. In principle, non-leaky FGTs can be implemented in a scaled down process without any special masks by using “double”-oxide transistors intended for providing devices that operate with higher supply voltages than general purpose devices. However, in practice the technology scaling poses several challenges which are addressed in this thesis. To provide a sufficiently wide-ranging survey, six prototype chips with varying complexity were implemented in four different DSM process nodes and investigated from this perspective. The focus is on non-leaky FGTs, but the presented autozeroing floating-gate amplifier (AFGA) demonstrates that leaky FGTs may also find a use. The simplest test structures contain only a few transistors, whereas the most complex experimental chip is an implementation of a spiking neural network (SNN) which comprises thousands of active and passive devices. More precisely, it is a fully connected (256 FGT synapses) two-layer spiking neural network (SNN), where the adaptive properties of FGT are taken advantage of. A compact realization of Spike Timing Dependent Plasticity (STDP) within the SNN is one of the key contributions of this thesis. Finally, the considerations in this thesis extend beyond CMOS to emerging nanodevices. To this end, one promising emerging nanoscale circuit element - memristor - is reviewed and its applicability for analog processing is considered. Furthermore, it is discussed how the FGT technology can be used to prototype computation paradigms compatible with these emerging two-terminal nanoscale devices in a mature and widely available CMOS technology.Siirretty Doriast

Low-cost, high-precision DAC design based on ordered element matching and verification against undesired operating points for analog circuits

Over the past 50 years, the integrated circuit (IC) industry has grown rapidly, following the famous ``Moore\u27s law. The process feature size keeps shrinking, whereby the performance of digital circuits is constantly enhanced and their cost constantly decreases. However, with the system integration and the development of system on chip (SoC), nearly all of today\u27s ICs contain analog/mixed-Signal circuits. Although a mixed-signal SoC is primarily digital, the analog circuit design and verification consume most of the resources, and the dominant source of IC breakdowns is attributable to the analog circuits. One important reason for the high cost and risk of breakdowns of analog circuits is that the technology advancement does not benefit many analog and mixed-signal circuits, and in fact imposes higher requirements on their performance. With process scaling, many important parameters of integrated circuit components degrade, which cause a drop in many key aspects of performance of analog circuits. Many analog circuits rely on matched circuit components (transistors, resistors, or capacitors) to achieve the required linearity performance; examples are amplifiers, digital-to-analog converters (DACs), etc. However, shrinking of the feature sizes increases the circuit components mismatch, thereby making it more difficult to maintain circuit accuracy. Therefore, to reduce the cost of analog circuit design, designers should propose new structures whose key performance can be improved by the technology scaling. In this dissertation, we propose a low-cost, high-precision DAC structure based on ordered element matching (OEM) theory. High matching accuracy can be achieved by applying OEM calibration to the resistors in unary weighted segments and calibrating the gain error between different segments by calibration DAC (CalDAC). As a design example to verify the proposed structure, a high-precision DAC is designed in a 130 nm Global Foundry (GF) CMOS process. The 130 nm GF process features high-density digital circuits and is a typical process which is constantly enhanced by the scaling of device dimensions and voltage supply; implementation of a high-precision DAC in such process is important to decreasing the costs of high-precision DAC designs. As a result, our proposed DAC structure is demonstrated to be able to significantly lower the cost of high-precision DAC design. Another reason for the high cost and risk of breakdowns of analog circuits arises from the complexity of analog circuit working states. Most digital circuits serve as logic functions, so that digital transistors work in only two states, either low or high. In contrast, analog circuits have much more complicated functions; they may work in multiple operating points, since various feedback approaches are applied in analog circuits to enhance their performance. Circuits with undetected operating points can be devastating, particularly when they are employed in critical applications such as automotive, health care, and military products. However, since the existing circuit simulators provide only a single operating point, recognizing the existence of undesired operating points depends largely on the experiences of designers. In some circuits, even the most experienced designers may not be aware that a circuit they designed has undesired operating points, which often go undetected in the standard simulations in the design process. To identify undesired operating points in an analog circuit and reduce its risk of breakdowns, a systematic verification method against undesired operating points in analog circuits is proposed in this dissertation. Unlike traditional methods of finding all operating points, this method targets only searches for voltage intervals containing undesired operating points. To achieve this, our method first converts the circuit into a corresponding graph and locates the break point to break all the positive feedback loops (PFLs). For one dimensional verification, divide and contraction algorithms could be applied to identify undesired operating points. Two dimensional vector field methods are used to solve the two dimensional verifications. Based on the proposed verification methods against undesired operating points, an EDA tool called ``ITV is developed to identify undesired operating points in analog and mixed-signal circuits. Simulation results show ITV to be effective and efficient in identifying undesired operating points in a class of commonly used benchmark circuits that includes bias generators, voltage references, temperature sensors, and op-amp circuits

Flexible Receivers in CMOS for Wireless Communication

Consumers are pushing for higher data rates to support more services that are introduced in mobile applications. As an example, a few years ago video-on-demand was only accessed through landlines, but today wireless devices are frequently used to stream video. To support this, more flexible network solutions have merged in 4G, introducing new technical problems to the mobile terminal. New techniques are thus needed, and this dissertation explores five different ideas for receiver front-ends, that are cost-efficient and flexible both in performance and operating frequency. All ideas have been implemented in chips fabricated in 65 nm CMOS technology and verified by measurements. Paper I explores a voltage-mode receiver front-end where sub-threshold positive feedback transistors are introduced to increase the linearity in combination with a bootstrapped passive mixer. Paper II builds on the idea of 8-phase harmonic rejection, but simplifies it to a 6-phase solution that can reject noise and interferers at the 3rd order harmonic of the local oscillator frequency. This provides a good trade-off between the traditional quadrature mixer and the 8- phase harmonic rejection mixer. Furthermore, a very compact inductor-less low noise amplifier is introduced. Paper III investigates the use of global negative feedback in a receiver front-end, and also introduces an auxiliary path that can cancel noise from the main path. In paper IV, another global feedback based receiver front-end is designed, but with positive feedback instead of negative. By introducing global positive feedback, the resistance of the transistors in a passive mixer-first receiver front-end can be reduced to achieve a lower noise figure, while still maintaining input matching. Finally, paper V introduces a full receiver chain with a single-ended to differential LNA, current-mode downconversion mixers, and a baseband circuity that merges the functionalities of the transimpedance amplifier, channel-select filter, and analog-to-digital converter into one single power-efficient block

Transmissores-recetores de baixa complexidade para redes óticas

Traditional coherent (COH) transceivers allow encoding of information in both quadratures and the two orthogonal polarizations of the electric field. Nevertheless, such transceivers used today are based on the intradyne scheme, which requires two 90o optical hybrids and four pairs of balanced photodetectors for dual-polarization transmission systems, making its overall cost unattractive for short-reach applications. Therefore, SSB methods with DD reception, commonly referred to as self-coherent (SCOH) transceivers, can be employed as a cost-effective alternative to the traditional COH transceivers. Nevertheless, the performance of SSB systems is severely degraded. This work provides a novel SCOH transceiver architecture with improved performance for short-reach applications. In particular, the development of phase reconstruction digital signal processing (DSP) techniques, the development of other DSP subsystems that relax the hardware requirement, and their performance optimization are the main highlights of this research. The fundamental principle of the proposed transceiver is based on the reception of the signal that satisfies the minimum phase condition upon DD. To reconstruct the missing phase information imposed by DD, a novel DCValue method exploring the SSB and the DC-Value properties of the minimum phase signal is developed in this Ph.D. study. The DC-Value method facilitates the phase reconstruction process at the Nyquist sampling rate and requires a low intensity pilot signal. Also, the experimental validation of the DC-Value method was successfully carried out for short-reach optical networks. Additionally, an extensive study was performed on the DC-Value method to optimize the system performance. In the optimization process, it was found that the estimation of the CCF is an important parameter to exploit all advantages of the DC-Value method. A novel CCF estimation technique was proposed. Further, the performance of the DC-Value method is optimized employing the rate-adaptive probabilistic constellation shaping.Os sistemas de transcetores coerentes tradicionais permitem a codificação de informação em ambas quadraturas e em duas polarizações ortogonais do campo elétrico. Contudo, estes transcetores utilizados atualmente são baseados num esquema intradino, que requer dois híbridos óticos de 90o e quatro pares de foto detetores para sistemas de transmissão com polarização dupla, fazendo com que o custo destes sistemas seja pouco atrativo para aplicações de curto alcance. Por isso, métodos de banda lateral única com deteção direta, também referidos como transcetores coerentes simplificados, podem ser implementados como uma alternativa de baixo custo aos sistemas coerentes tradicionais. Contudo, o desempenho de sistemas de banda lateral única tradicionais é gravemente degradado pelo batimento sinal-sinal. Nesta tese foi desenvolvida uma nova arquitetura de transcetor coerente simplificada com um melhor desempenho para aplicações de curto alcance. Em particular, o desenvolvimento de técnicas de processamento digital de sinal para a reconstrução de fase, bem como de outros subsistemas de processamento digital de sinal que minimizem os requerimentos de hardware e a sua otimização de desempenho são o foco principal desta tese. O princípio fundamental do transcetor proposto é baseado na receção de um sinal que satisfaz a condição mínima de fase na deteção direta. Para reconstruir a informação de fase em falta causada pela deteção direta, um novo método de valor DC que explora sinais de banda lateral única e as propriedades DC da condição de fase mínima é desenvolvido nesta tese. O método de valor DC facilita a reconstrução da fase à frequência de amostragem de Nyquist e requer um sinal piloto de baixa intensidade. Além disso, a validação experimental do método de valor DC foi executada com sucesso em ligações óticas de curto alcance. Adicionalmente, foi realizado um estudo intensivo do método de valor DC para otimizar o desempenho do sistema. Neste processo de otimização, verificou-se que o fator de contribuição da portadora é um parâmetro importante para explorar todas as vantagens do método de valor DC. Neste contexto, é proposto um novo método para a sua estimativa. Por último, o desempenho do método de valor DC é otimizado recorrendo a mapeamento probabilístico de constelação com taxa adaptativa.Programa Doutoral em Engenharia Eletrotécnic

Ultra-small low power temperature-to-digital converter and verification methods of analog circuit with Trojan states

Accurate, small and low-power CMOS temperature sensors designed for multi-position temperature monitoring of power management in multi-core processors are proposed. The temperature sensors utilize the temperature characteristics of the threshold voltage of a MOS transistors to sense temperature and are highly linear from 60°C to 90°C. This is the temperature range needed for the power management applications where temperature sensors are strategically placed at multiple locations in each core to protect the processor from temperature-induced reliability degradation. A temperature-to-digital converter (TDC) that does not require either a reference generator or an ADC is also introduced, and it exhibits low supply sensitivity, small die area, and low power consumption. Both analog threshold voltage based temperature sensor and a prototype TDC designed to support multi-position thermal-sensing for power management applications from 60°C to 90°C are implemented in an IBM 0.13μm CMOS process with a 1.2V power supply. A new verification approach with several variants for identifying the number of stable equilibrium points in supply-insensitive bias generators, references, and temperature sensors based upon self-stabilized feedback loops is introduced. This provides a simple and practical method for determining if these circuits require a “start-up” circuit and, if needed, for verifying that the startup circuit is effective at eliminating undesired stable equilibrium points in the presence of process and temperature variations. These undesired stable equilibrium points are often referred to as Trojan states. It will be shown that some widely used approaches for verification do not guarantee Trojan states have been removed. Some of the methods introduced appear to be more practical to work with than others. A group of benchmark circuit with Trojan states will be introduced and used to demonstrate the effectiveness of the new method

A 10-bit 4 MS/s SAR ADC with Fully-Dynamic Duty-Cycled Input Driver

This paper presents a duty-cycled input driver for a SAR ADC. Being a discrete-time system, the SAR ADC requires an accurate input signal only at its sampling moment. This motivates the use of a duty-cycled input driver which can be turned off during the conversion phase to save power. In this way, the power consumption of the SAR ADC together with its input driver becomes fully dynamic. This idea is applied to a 10-bit 4 MS/s SAR ADC with unity-gain input drivers. Fabricated in 65 nm CMOS, the prototype achieves 8.9 ENOB and 69.9 dB SFDR while consuming 35.0 µW. This leads to a Walden FoM of 18.3 fJ/conversion-step for the ADC including driver.</p