Flight deck automation: Promises and realities

Issues of flight deck automation are multifaceted and complex. The rapid introduction of advanced computer-based technology onto the flight deck of transport category aircraft has had considerable impact both on aircraft operations and on the flight crew. As part of NASA's responsibility to facilitate an active exchange of ideas and information among members of the aviation community, a NASA/FAA/Industry workshop devoted to flight deck automation, organized by the Aerospace Human Factors Research Division of NASA Ames Research Center. Participants were invited from industry and from government organizations responsible for design, certification, operation, and accident investigation of transport category, automated aircraft. The goal of the workshop was to clarify the implications of automation, both positive and negative. Workshop panels and working groups identified issues regarding the design, training, and procedural aspects of flight deck automation, as well as the crew's ability to interact and perform effectively with the new technology. The proceedings include the invited papers and the panel and working group reports, as well as the summary and conclusions of the conference

Survey on Instruction Selection: An Extensive and Modern Literature Review

Instruction selection is one of three optimisation problems involved in the code generator backend of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation. Despite on-going research since the late 1960s, the last, comprehensive survey on the field was written more than 30 years ago. As new approaches and techniques have appeared since its publication, this brings forth a need for a new, up-to-date review of the current body of literature. This report addresses that need by performing an extensive review and categorisation of existing research. The report therefore supersedes and extends the previous surveys, and also attempts to identify where future research should be directed.Comment: Major changes: - Merged simulation chapter with macro expansion chapter - Addressed misunderstandings of several approaches - Completely rewrote many parts of the chapters; strengthened the discussion of many approaches - Revised the drawing of all trees and graphs to put the root at the top instead of at the bottom - Added appendix for listing the approaches in a table See doc for more inf

Diagnostic de fertilité des sols et conseils en fertilisation des principales cultures réunionnaises

Confronté à la demande des agriculteurs et des institutions du développement, le Cirad-Réunion s'est préoccupé très tôt de définir des normes d'interprétation des analyses de sol pour élaborer des conseils en fertilisation. Un système expert opérationnel d'interprétation automatique des analyses de sol et de conseil en fertilisation en résulte. Ce système repose sur une classification préalable des sols en fonction de leurs origines morphopédologiques et de leurs caractéristiques chimiques. Des clefs d'interprétation spécifiques à chaque type de sol ainsi définies autorisent un diagnostic de fertilité pour l'acidité, les éléments minéraux majeurs et les oligoéléments. Ces diagnostics sont utilisés, d'une part pour rectifier les principales carences du sol par un amendement approprié et, d'autre part pour élaborer un conseil en fertilisation d'entretien adapté aux besoins des cultures. Le système expert a été conçu pour la canne à sucre, principale culture de l'île. Il a été ensuite étendu aux graminées fourragères, à l'ananas et au bananier. (Résumé d'auteur

Storage constraint satisfaction for embedded processor compilers

Increasing interest in the high-volume high-performance embedded processor market motivates the stand-alone processor world to consider issues like design flexibility (synthesizable processor core), energy consumption, and silicon efficiency. Implications for embedded processor architectures and compilers are the exploitation of hardware acceleration, instruction-level parallelism (ILP), and distributed storage files. In that scope, VLIW architectures have been acclaimed for their parallelism in the architecture while orthogonality of the associated instruction sets is maintained. Code generation methods for such processors will be pressured towards an efficient use of scarce resources while satisfying tight real-time constraints imposed by DSP and multimedia applications. Limited storage (e.g. registers) availability poses a problem for traditional methods that perform code generation in separate stages, e.g. operation scheduling followed by register allocation. This is because the objectives of scheduling and register allocation cause conflicts in code generation in several ways. Firstly, register reuse can create dependencies that did not exist in the original code, but can also save spilling values to memory. Secondly, while a particular ordering of instructions may increase the potential for ILP, the reordering due to instruction scheduling may also extend the lifetime of certain values, which can increase the register requirement. Furthermore, the instruction scheduler requires an adequate number of local registers to avoid register reuse (since reuse limits the opportunity for ILP), while the register allocator would prefer sufficient global registers in order to avoid spills. Finally, an effective scheduler can lose its achieved degree of instruction-level parallelism when spill code is inserted afterwards. Without any communication of information and cooperation between scheduling and storage allocation phases, the compiler writer faces the problem of determining which of these phases should run first to generate the most efficient final code. The lack of communication and cooperation between the instruction scheduling and storage allocation can result in code that contains excess of register spills and/or lower degree of ILP than actually achievable. This problem called phase coupling cannot be ignored when constraints are tight and efficient solutions are desired. Traditional methods that perform code generation in separate stages are often not able to find an efficient or even a feasible solution. Therefore, those methods need an increasing amount of help from the programmer (or designer) to arrive at a feasible solution. Because this requires an excessive amount of design time and extensive knowledge of the processor architecture, there is a need for automated techniques that can cope with the different kinds of constraints during scheduling. This thesis proposes an approach for instruction scheduling and storage allocation that makes an extensive use of timing, resource and storage constraints to prune the search space for scheduling. The method in this approach supports VLIW architectures with (distributed) storage files containing random-access registers, rotating registers to exploit the available ILP in loops, stacks or fifos to exploit larger storage capacities with lower addressing costs. Potential access conflicts between values are analyzed before and during scheduling, according to the type of storage they are assigned to. Using constraint analysis techniques and properties of colored conflict graphs essential information is obtained to identify the bottlenecks for satisfying the storage file constraints. To reduce the identified bottlenecks, this method performs partial scheduling by ordering value accesses such that to allow a better reuse of storage. Without enforcing any specific storage assignment of values, the method continues until it can guarantee that any completion of the partial schedule will also result in a feasible storage allocation. Therefore, the scheduling freedom is exploited for satisfaction of storage, resource, and timing constraints in one phase

On Fault Tolerance Methods for Networks-on-Chip

Technology scaling has proceeded into dimensions in which the reliability of manufactured devices is becoming endangered. The reliability decrease is a consequence of physical limitations, relative increase of variations, and decreasing noise margins, among others. A promising solution for bringing the reliability of circuits back to a desired level is the use of design methods which introduce tolerance against possible faults in an integrated circuit. This thesis studies and presents fault tolerance methods for network-onchip (NoC) which is a design paradigm targeted for very large systems-onchip. In a NoC resources, such as processors and memories, are connected to a communication network; comparable to the Internet. Fault tolerance in such a system can be achieved at many abstraction levels. The thesis studies the origin of faults in modern technologies and explains the classification to transient, intermittent and permanent faults. A survey of fault tolerance methods is presented to demonstrate the diversity of available methods. Networks-on-chip are approached by exploring their main design choices: the selection of a topology, routing protocol, and flow control method. Fault tolerance methods for NoCs are studied at different layers of the OSI reference model. The data link layer provides a reliable communication link over a physical channel. Error control coding is an efficient fault tolerance method especially against transient faults at this abstraction level. Error control coding methods suitable for on-chip communication are studied and their implementations presented. Error control coding loses its effectiveness in the presence of intermittent and permanent faults. Therefore, other solutions against them are presented. The introduction of spare wires and split transmissions are shown to provide good tolerance against intermittent and permanent errors and their combination to error control coding is illustrated. At the network layer positioned above the data link layer, fault tolerance can be achieved with the design of fault tolerant network topologies and routing algorithms. Both of these approaches are presented in the thesis together with realizations in the both categories. The thesis concludes that an optimal fault tolerance solution contains carefully co-designed elements from different abstraction levelsSiirretty Doriast

"Hurlements en faveur de Guy"

Die vorliegende Arbeit beschäftigt sich mit der Person und dem Künstler Guy Debord und durchleuchtet den Zusammenhang zwischen seinem Leben und Werk im zeitgeschichtlichen Kontext des 20. Jahrhunderts. Durch die lettristische Bewegung inspiriert, gründete er in Paris Anfang der 1950er Jahre die Lettristische Internationale und folgend die Situationistische Internationale, die auf internationaler Ebene agierte und Künstler wie den Maler Asger Jorn oder den Architekten Constant zu ihren Mitgliedern zählte. Guy Debord selbst war nicht nur der theoretische Kopf der Gruppierungen, seine Rolle als (siutationistischer) Filmemacher und Revolutionär des Avantgarde-Kinos wird anhand mehrerer Filmbeispiele aufgezeigt. War das primäre Ziel das avantgardischte Konzept die Aufhebung der Trennung von Leben, Kunst und Politik, so gelang es Guy Debord – am Schnittpunkt zwischen Politik und Kunst - diesem Konzept zumindest in seinem Leben treu zu bleiben. In der paradoxen Rezeption seines künstlerischen Erbes wird die Bedeutung und Wirkung seines Schaffens ersichtlich. Die Arbeit gliedert sich in drei Haupteile: Im ersten wird seine Biografie in den zeitgeschichtlichen Kontext gestellt, im zweiten wird seine theoretische und filmische Arbeit erläutert, und im dritten Teil wird ein Abriss der Rezeptionsgeschichte dargelegt, mit dem Schwerpunkt der Inhaltsanalyse des Theaterstücks "Scanner", das Guy Debord als Inhalt hat und als beispielhaft für die aktuelle Rezeptionsweise in Frankreich gesehen werden kann

Fertilité des sols et conseil en fertilisation, Système expert d'inerprétation des analyses chimiques des sols réunionnais.amendement et conseil en fertilisation pour la canne à sucre, les graminées fourragères, l'ananas et le bananier

Le laboratoire d'analyse des sols du CIRAD Réunion dispose d'un système expert écrit sous FOX PRO @, qui procède à l'interprétation automatique des résultats d'analyse, à l'élaboration de conseils en fumure de fond ainsi qu'aux conseils en fertilisation d'entretien pour la canne à sucre, les graminées fourragères, I'ananas et le bananier. Ce système édite automatiquement les bulletins d'analyse où figurent un diagnostic de fertilité du sol et des conseils en fertilisation. Les cinq dernières années de fonctionnement démontrent la cohérence du système.Le diagnostic de fertilité est basé sur des seuils qui permettent de qualifier les résultats de l'analyse chimique. Les seuils sont spécifiques à chacun des six types de sol réunionnais : ferrallitique, andique perhydraté, andique non perhydraté, vertique, brun et brun andique. Ces sols ont été identifiés et localisés à partir des unités morphopédologiques et de la distribution des caractéristiques chimiques de 15.000 analyses. La localisation cartographique de l'échantillon à analyser permet au système expert d'identifier le type de sol et de charger la grille d'interprétation qui lui est adaptée. Des informations spécifiques aux cultures sont ensuite utilisées par le système pour calculer des conseils en fumure de fond et d'entretien adaptés aux besoins des cultures et au niveau de production escompté. Les résultats sont traduits sur les bulletins d'analyse par des plans de fumure faisant intervenir lorsque nécessaire le calendrier d'apport et les doses traduites en engrais commercial.Une analyse détaillée et critique des bases du système expert, de son fonctionnement et de l'application des résultats est développée par les auteurs parallèlement à des propositions d'amélioration. (Résumé d'auteur