AUTOMATED WRAPPER DESIGN FOR ISCAS ’89 BENCHMARK CIRCUITS

System-on-chip (SOC) enables the reuse of existing IP blocks in a system, thereby making it possible to design complex systems within a short period of time. With the complexity of the design comes the problem of testing the SOC. A typical SOC can integrate many modules, therefore making it difficult to test these individual modules by accessing from the primary interfaces of the chip. To aleviate this test access issue for SOC‟s, the IEEE 1500 standard has been introduced. There are commercial tools from main EDA players such as Synopsys that can help with the insertion of the IEEE 1500 wrapper. However, most researchers have no access to the expensive tool. Even if they do, the tools are protected so they do not allow researchers access to the internal features to explore potential enhancements. There is no open source tools that can assist test researchers with the 1500 wrapper insertion. In this thesis, we illustrate our effort at automating the IEEE 1500 wrapper insertion. The design of the IEEE 1500 wrapper is done in Verilog and the automation is done using the Perl scripting language. The inserted wrapper modules are validated and an efficient approach of executing wrapper external tests is also illustrated in this thesis

A Hardware Security Solution against Scan-Based Attacks

Scan based Design for Test (DfT) schemes have been widely used to achieve high fault coverage for integrated circuits. The scan technique provides full access to the internal nodes of the device-under-test to control them or observe their response to input test vectors. While such comprehensive access is highly desirable for testing, it is not acceptable for secure chips as it is subject to exploitation by various attacks. In this work, new methods are presented to protect the security of critical information against scan-based attacks. In the proposed methods, access to the circuit containing secret information via the scan chain has been severely limited in order to reduce the risk of a security breach. To ensure the testability of the circuit, a built-in self-test which utilizes an LFSR as the test pattern generator (TPG) is proposed. The proposed schemes can be used as a countermeasure against side channel attacks with a low area overhead as compared to the existing solutions in literature

A Communications Testbed for Testing Power Electronic Agent Systems

As power electronic system (PES) continue to incorporate complex intra-system communication, understanding and characterizing this communication has become a complex task. Knowing how a system’s communication will behave is vital to ensuring proper operation of these systems. This thesis proposes and outlines a communication testbed that streamlines the development and testing of the communications between the components of PES, and further presents the characterization of communication protocol utilized in these multi-agent PESs. These communication protocols include MQTT, Modbus, or User Datagram Protocol (UDP). Understanding the different behavior of these protocols presents is paramount for the design of PESs

Studies on Core-Based Testing of System-on-Chips Using Functional Bus and Network-on-Chip Interconnects

The tests of a complex system such as a microprocessor-based system-onchip (SoC) or a network-on-chip (NoC) are difficult and expensive. In this thesis, we propose three core-based test methods that reuse the existing functional interconnects-a flat bus, hierarchical buses of multiprocessor SoC's (MPSoC), and a N oC-in order to avoid the silicon area cost of a dedicated test access mechanism (TAM). However, the use of functional interconnects as functional TAM's introduces several new problems. During tests, the interconnects-including the bus arbitrator, the bus bridges, and the NoC routers-operate in the functional mode to transport the test stimuli and responses, while the core under tests (CUT) operate in the test mode. Second, the test data is transported to the CUT through the functional bus, and not directly to the test port. Therefore, special core test wrappers that can provide the necessary control signals required by the different functional interconnect are proposed. We developed two types of wrappers, one buffer-based wrapper for the bus-based systems and another pair of complementary wrappers for the NoCbased systems. Using the core test wrappers, we propose test scheduling schemes for the three functionally different types of interconnects. The test scheduling scheme for a flat bus is developed based on an efficient packet scheduling scheme that minimizes both the buffer sizes and the test time under a power constraint. The schedulingscheme is then extended to take advantage of the hierarchical bus architecture of the MPSoC systems. The third test scheduling scheme based on the bandwidth sharing is developed specifically for the NoC-based systems. The test scheduling is performed under the objective of co-optimizing the wrapper area cost and the resulting test application time using the two complementary NoC wrappers. For each of the proposed methodology for the three types of SoC architec .. ture, we conducted a thorough experimental evaluation in order to verify their effectiveness compared to other methods

A Method to Support Diagnostics of Dynamic Faults in Networks of Interconnections

The article is devoted to the method facilitating the diagnostics of dynamic faults in networks of interconnection in systems-on-chips. It shows how to reconstruct the erroneous test response sequence coming from the faulty connection based on the set of signatures obtained as a result of multiple compaction of this sequence in the MISR register with programmable feedback. The Chinese reminder theorem is used for this purpose. The article analyzes in detail the various hardware realizations of the discussed method. The testing time associated with each proposed solution was also estimated. Presented method can be used with any type of test sequence and test pattern generator. It is also easily scalable to any number of nets in the network of interconnections. Moreover, it supports finding a trade-off between area overhead and testing time

Power Electronics Technology for Large-Scale Renewable Energy Generation

Grid integration of renewable energy (REN) requires efficient and reliable power conversion stages, particularly with an increasing demand for high controllability and flexibility seen from the grid side. Underpinned by advanced control and information technologies, power electronics converters play an essential role in large-scale REN generation. However, the use of power converters has also exposed several challenges in conventional power grids, e.g., reducing the system inertia. In this article, grid integration using power electronics is presented for large-scale REN generation. Technical issues and requirements are discussed with a special focus on grid-connected wind, solar photovoltaic, and energy storage systems. In addition, the core of the energy generation and conversion—control for individual power converters (e.g., general current control) and for the system level (e.g., coordinated operation of large-scale energy systems)—is briefly discussed. Future research perspectives are then presented, which further advance large-scale REN generation technologies by incorporating more power electronics systems

Measurement Platform for Latency Characterization of Wide Area Monitoring, Protection and Control Systems

Wide area monitoring, protection and control (WAMPAC) systems have emerged as a critical technology to improve the reliability, resilience, and stability of modern power grids. They are based on phasor measurement unit (PMU) technology and synchronized monitoring on a wide area. Since these systems are required to make rapid decisions and control actions on the grid, they are characterized by stringent time constraints. For this reason, the latency of WAMPAC systems needs to be appropriately assessed. Following this necessity, this article presents the design and implementation of a measurement platform that allows latency characterization of different types of WAMPAC systems in several operating conditions. The proposed WAMPAC Characterizer has been metrologically characterized through a WAMPAC Emulator and then used to measure the latency of a WAMPAC system based on an open-source platform frequently used by transmission system operators (TSOs) for the implementation of their PMU-based wide area systems

Intelligent energy management agent for a parallel hybrid vehicle

This dissertation proposes an Intelligent Energy Management Agent (IEMA) for parallel hybrid vehicles. A key concept adopted in the development of an IEMA is based on the premise that driving environment would affect fuel consumption and pollutant emissions, as well as the operating modes of the vehicle and the driver behavior do. IEMA incorporates a driving situation identification component whose role is to assess the driving environment, the driving style of the driver, and the operating mode (and trend) of the vehicle using long and short term statistical features of the drive cycle. This information is subsequently used by the torque distribution and charge sustenance components of IEMA to determine the power split strategy, which is shown to lead to improved fuel economy and reduced emissions

NeuroHub Networking Integration: Time Synchronization Device for Multimodal Brain Imaging and Hyperscanning Research

Significant progress has been made over the last decades in understanding the physiological and neural bases of cognitive processes and behavior. The advent of new and improved sensors enables monitoring the human body and brain activity in natural environments, with cost-effective, mobile and wearable form factor systems. As neuroimaging and brain sensing technologies are further developed, there's an expanding interest for using multiple systems concurrently on i) the same brain: multimodal/hybrid measurements for better identification of neurophysiological markers, and ii) multiple brains: hyperscanning for novel investigations of brain functions during social interactions. Particularly for functional neuroimaging, such as Functional Near Infrared Spectroscopy (fNIRS) and Electroencephalography (EEG), precise time synchronization of experimental events with acquired datasets is necessary for proper analysis and interpretation of results. However, there are currently no standards for interoperability and neuroimaging systems have many different designs and interfaces. Furthermore, it is often cumbersome to come up with a custom solution to each new research setup based on the devices involved. The original NeuroHub, a plug-and-play time synchronization device developed at Drexel University, attempted to alleviate some of the complications associated with custom setups and time synchronization. The original NeuroHub relayed any incoming signal to one of its four serial ports, TTL port, and parallel port, to all other ports on the device and can be connected to multiple sending/listening devices or computers. Although one or more of these legacy ports are present in various neuroimaging systems, modern computing systems require more sophisticated alternatives. This thesis proposes a solution and improvement to the original NeuroHub, by incorporating time synchronization over a network as an information transfer layer. The network solution enables more flexible experimental configurations and expands the compatible plug-and-play system range. Moreover, this new approach eliminates the need for multiple wires, while still being able to service large number of clients. The new NeuroHub is also able to directly interface with typical RS-232 serial ports and offers the best of both worlds - ability to interface with network and legacy hardware ports for complete customizability, flexibility and backward compatibility. The new NeuroHub network module consists of a Raspberry Pi Model 1B fitted with a serial port add-on board. The device transmits any event markers received from either networked or serial ports and relays them to the other opened ports. Verification testing confirmed that the device transmits with 100% accuracy and the latency to send a byte from one computer to the other via the network module was minimal, ranging from sub-millisecond speeds to 7 ms depending on the use of serial ports, baud-rate, and configuration order. The new NeuroHub network module was tested in Brain Compute Interface (BCI) setups using OpenViBE as a stimulus presenter and EEG data recording, with COBI Studio as the fNIRS data recording software to receive markers all through NeuroHub. This simple use case demonstrates the utility of the new NeuroHub for simplification of complex functional neuroimaging, neuroergonomics and BCI research experimental setups.M.S., Biomedical Engineering -- Drexel University, 201