A 334µW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Extended Version

The hard mathematical problems that assure the security of our current public-key cryptography (RSA, ECC) are broken if and when a quantum computer appears rendering them ineffective for use in the quantum era. Lattice based cryptography is a novel approach to public key cryptography, of which the mathematical investigation (so far) resists attacks from quantum computers. By choosing a module learning with errors (MLWE) algorithm as the next standard, National Institute of Standard \& Technology (NIST) follows this approach. The multiplication of polynomials is the central bottleneck in the computation of lattice based cryptography. Because public key cryptography is mostly used to establish common secret keys, focus is on compact area, power and energy budget and to a lesser extent on throughput or latency. While most other work focuses on optimizing number theoretic transform (NTT) based multiplications, in this paper we highly optimize a Toom-Cook based multiplier. We demonstrate that a memory-efficient striding Toom-Cook with lazy interpolation, results in a highly compact, low power implementation, which on top enables a very regular memory access scheme. To demonstrate the efficiency, we integrate this multiplier into a Saber post-quantum accelerator, one of the four NIST finalists. Algorithmic innovation to reduce active memory, timely clock gating and shift-add multiplier has helped to achieve 38\% less power than state-of-the art PQC core, 4 $\times$ less memory, 36.8\% reduction in multiplier energy and 118$\times$ reduction in active power with respect to state-of-the-art Saber accelerator (not silicon verified). This accelerator consumes $0.158mm^2$ active area which is lowest reported till date despite process disadvantages of the state-of-the-art designs

Electrochemically deposited germanium on silicon and its crystallization by rapid melting growth

It is well known that continuous miniaturization of transistors tends to create several problems such as current leakage, short channel effect, etc. Therefore, introduction of new channel material with higher carrier mobilities such as Germanium (Ge) is suggested to overcome this physical limitation and also to improve the performance of conventional transistors in chips. Basically, there are several techniques to grow Ge such as Chemical Vapour Deposition (CVD) and Molecular Beam Epitaxy (MBE) system. However, these processes require high vacuum environment, highly depend on such hard-to-control variables as well as costly. Therefore, an alternative method that practically cheaper to grow Ge utilizing electrochemical and rapid melting technique is investigated here. In this thesis, a systematic study of electrochemical deposition of Ge on Silicon (Si) substrate is outlined. Results show the unwanted Germanium Dioxide (GeO2) tends to form in the air-exposed process and germanium tetrachloride:dipropylene glycol (GeCl4:C6H14O3) electrolyte. Therefore, a Nitrogen (N2) controlled ambient is preferable. The uniform amorphous Ge film on Si (100) substrate was successfully obtained at the optimum current density of 20 mAcm-2 in germanium tetrachloride:propylene glycol (GeCl4:C3H8O2) electrolyte. Crystallization of electrodeposited Ge on Si (100) was demonstrated by rapid melting process. Effect of different annealing temperatures from 1000 to 1100 oC has also been studied. Raman spectra and Electron Backscattering Diffraction (EBSD) result confirmed that the grown Ge was highly oriented with the crystal orientation identical to that of Si (100) substrate at all annealing temperature tested. Based on depth profile from Auger Electron Spectroscopy (AES) measurement and Raman spectra, it was found that Si-Ge mixing occurred upon rapid melting process, particularly at near the Si-Ge interface caused by atoms diffusion. Calculated Si fraction diffused into Ge region in the Si-Ge mixing was high at higher annealing temperature that shows good agreement with solidus curve of Ge-Si equilibrium phase diagram. Correspondingly, the amount of Ge diffused into Si region also increased as annealing temperature increased. The result also shows that the tensile strain turns from high to low with the increase of annealing temperature. In addition, it drastically becomes more compressive as the depth is approaching the interface of Ge and Si. The difference in thermal expansion coefficient is a possible cause to generate such strain behaviour. For applications, the presence of strain in channel will improve the transistor performance by enhancing the carrier mobility. In conclusion, this study proves that electrochemical deposition and rapid melting growth technique are promising methods for synthesizing crystalline Ge and significantly contribute to the improvement of carrier mobility. It is expected that high performance Complementary Metal Oxide Semiconductor (CMOS) transistor scaling and Moore’s Law will continue in the future through new materials introduction in the transistor structure and by incorporating significantly appropriate levels of strain and composition of Ge/Si in the channel

Circuits and Systems Advances in Near Threshold Computing

Modern society is witnessing a sea change in ubiquitous computing, in which people have embraced computing systems as an indispensable part of day-to-day existence. Computation, storage, and communication abilities of smartphones, for example, have undergone monumental changes over the past decade. However, global emphasis on creating and sustaining green environments is leading to a rapid and ongoing proliferation of edge computing systems and applications. As a broad spectrum of healthcare, home, and transport applications shift to the edge of the network, near-threshold computing (NTC) is emerging as one of the promising low-power computing platforms. An NTC device sets its supply voltage close to its threshold voltage, dramatically reducing the energy consumption. Despite showing substantial promise in terms of energy efficiency, NTC is yet to see widescale commercial adoption. This is because circuits and systems operating with NTC suffer from several problems, including increased sensitivity to process variation, reliability problems, performance degradation, and security vulnerabilities, to name a few. To realize its potential, we need designs, techniques, and solutions to overcome these challenges associated with NTC circuits and systems. The readers of this book will be able to familiarize themselves with recent advances in electronics systems, focusing on near-threshold computing

Cross-Correlator Implementations Enabling Aperture Synthesis for Geostationary-Based Remote Sensing

An ever-increasing demand for weather prediction and high climate modelling accuracy drives the need for better atmospheric data collection. These demands include better spatial and temporal coverage of mainly humidity and temperature distributions in the atmosphere. A new type of remote sensing satellite technology is emerging, originating in the field of radio astronomy where telescope aperture upscaling could not keep up with the increasing demand for higher resolution. Aperture synthesis imaging takes an array of receivers and emulates apertures extending way beyond what is possible with any single antenna. In the field of Earth remote sensing, the same idea could be used to construct satellites observing in the microwave region at a high resolution with foldable antenna arrays. If placed in a geostationary orbit, these could produce images with high temporal resolution, however, such altitudes make the resolution requirement and, hence, signal processing very demanding. The relentless development in miniaturization of integrated circuits has in recent years made the concept of high resolution aperture synthesis imaging aboard a satellite platform viable.The work presented in this thesis addresses the challenge of performing the vital signal processing required aboard an aperture synthesis imager; namely the cross-correlation. A number of factors make the application challenging; the very restrictive power budgets of satellites, the immense amount of signal processing required for larger arrays, and the environmental aspects of in-space operation. The design, fabrication and evaluation of two cross-correlator application-specific integrated circuits (ASICs), one analog-to-digital converter (ADC) ASIC and one complete cross-correlator back-end is presented. Design concepts such as clocking schemes, data routing and reconfigurable accuracy for the cross-correlators and offset compensation and interfacing of the ADCs are explained. The underlying reasons for design choices as well as ASIC design and testing methodologies are described. The ASICs are put into their proper context as part of an interferometer system, and some different cross-correlator back-end architectures are explored.The result from this work is a very power-efficient, high-performance way of constructing cross-correlators which clearly demonstrates the viability of space-borne microwave imaging interferometer back-ends

WIRELESS SENSOR NODE WITH LOW-POWER SENSING

Wireless sensor network consists of a large number of simply sensor nodes that collect information from the external environment by sensors, process the information, and communicate with other neighboring nodes in the network. Usually sensor nodes operate with exhaustible batteries unattended. Since manual replacement or recharging the batteries is not an easy, desirable and always possible task, the power consumption becomes a very important issue in the development of these networks. The total power consumption of a node is a result of all steps of operation: sensing, data processing and radio transmission. In this work we focus on the impact of sensing hardware on the total power consumption of a sensor node. Firstly, we describe the structure of sensor node architecture, identify its key energy consumption sources, and introduce an energy model for the sensing subsystem as building block of a node. Secondly, with aim to reduce energy consumption of a node we propose implementation of two power-saving techniques: duty-cycling and power-gating. Duty-cycling is effective at system level. It is used for switching a node between active and sleep mode (with duty-cycle factor of 1% reduction of in dynamic energy consumption is achieved). Power-gating is implemented at circuit level with goal to decrease a power loss due to leakage current (in our design, a reduction of dynamic and static energy consumption of off-chip sensor elements as constituents of sensing hardware within a node of is achieved). Our MATLAB simulation results suggest that in total for a sensing hardware thanks to involving of duty-cycling and power-gating secures a three order of magnitude reduction ( ) in energy consumption can be achieved compared to a node architecture in which the implementation of  both energy saving techniques are omitted

Analog‐to‐Digital Conversion for Cognitive Radio: Subsampling, Interleaving, and Compressive Sensing

This chapter explores different analog-to-digital conversion techniques that are suitable to be implemented in cognitive radio receivers. This chapter details the fundamentals, advantages, and drawbacks of three promising techniques: subsampling, interleaving, and compressive sensing. Due to their major maturity, subsampling- and interleaving-based systems are described in further detail, whereas compressive sensing-based systems are described as a complement of the previous techniques for underutilized spectrum applications. The feasibility of these techniques as part of software-defined radio, multistandard, and spectrum sensing receivers is demonstrated by proposing different architectures with reduced complexity at circuit level, depending on the application requirements. Additionally, the chapter proposes different solutions to integrate the advantages of these techniques in a unique analog-to-digital conversion process

Aging prediction methodology for digital circuits

Dissertação de mest., Engenharia Eléctrica e Electrónica (Tecnologias de Informação e Telecomunicações), Instituto Superior de Engenharia, Univ. do Algarve, 2012Com a constante miniaturização da tecnologia de circuitos integrados CMOS, diversos problemas de fiabilidade e performance estão a tornar-se críticos à medida que a escala continua a ser reduzida. Efeitos a longo prazo, como o NBTI, TDDB, HCI, MS, etc, degradam os parâmetros físicos dos transístores CMOS e com consequências nas propriedades eléctricas dos semicondutores. O fenómeno NBTI é considerado o efeito dominante no processo de degradação por envelhecimento dos CMOS e influencia a operação dos transístores PMOS. Os efeitos degradantes do NBTI são manifestados na degradação da corrente de dreno, nas capacidades, na transcondutância e na tensão limiar de condução (Vth) dos transístores PMOS, mas pode ser representada simplesmente como um incremento no |Vth| ao longo do tempo. Esta degradação é chamada de envelhecimento e estes efeitos cumulativos têm um grande impacto na performance do circuito, especialmente se ocorrerem outras variações paramétricas, como as variações de processo, tensão de alimentação e temperatura. O trabalho apresentado nesta dissertação tem por objectivo desenvolver uma metodologia para prever a degradação na performance dos circuitos digitais CMOS na presença de efeitos de envelhecimento por NBTI. Uma biblioteca genérica SPICE de CMOS foi também definida de forma a usar vários modelos preditivos de tecnologias (PTM). A previsão do envelhecimento é baseada em cálculos das probabilidades dos transístores PMOS terem uma polarização negativa em VGS, na modelação das correspondentes variações em Vth para cada transístor e nas simulações SPICE para medir a degradação na performance. A automatização da metodologia é materializada numa nova ferramenta de software chamada AgingCalc, desenvolvida no âmbito desta tese de mestrado. A metodologia de previsão de envelhecimento proposta é demonstrada através de simulações em circuitos de referência em tecnologias de 130nm a 16nm, usando modelos PTM