TCAD-Machine learning framework for device variation and operating temperature analysis with experimental demonstration

This work, for the first time, experimentally demonstrates a TCAD-Machine Learning (TCAD-ML) framework to assist the analysis of device-to-device variation and operating (ambient) temperature without the need of physical quantities extraction. The ML algorithm used in this work is the Principal Component Analysis (PCA) followed by third order polynomial regression. After calibrated to limited \u27expensive\u27 experimental data, \u27low cost\u27 TCAD simulation is used to generate a large amount of device data to train the ML model. The ML was then used to identify the root cause of device variation and operating temperature from any given experimental current-voltage (I-V) characteristics. We applied this framework to study the ultra-wide-bandgap gallium oxide (Ga2O3) Schottky barrier diode (SBD), an emerging device technology that holds great promise for temperature sensing, RF, and power applications in harsh environments. After calibration, over 150,000 electrothermal TCAD simulations are performed with random variation of physical parameters (anode effective work function, drift layer doping, and drift layer thickness) and operating temperature. An ML model is trained using these TCAD data and we found 1,000-10,000 TCAD data can train an accurate machine. We show that without physical quantities extraction, performing PCA is essential for the TCAD trained ML model to be applicable to analyze experimental characteristics. The physical parameters and temperatures predicted by the ML model show good agreement with experimental analysis. Our TCAD-ML framework shows great promise to accelerate the development of new device technologies with a significantly more efficient process of material and device experimentation

Variability and power enhancement of current controlled resistive switching devices

Producción CientíficaIn this work, the unipolar resistive switching behaviour of Ni/HfO2/Si(n+) devices is studied. The structures are characterized using both current and voltage sweeps, with the device resistance and its cycle-to-cycle variability being analysed in each case. Experimental measurements indicate a clear improvement on resistance states stability when using current sweeps to induce both set and reset processes. Moreover, it has been found that using current to induce these transitions is more efficient than using voltage sweeps, as seen when analysing the device power consumption. The same results are obtained for devices with a Ni top electrode and a bilayer or pentalayer of HfO2/Al2O3 as dielectric. Finally, kinetic Monte Carlo and compact modelling simulation studies are performed to shed light on the experimental results.Junta de Andalucía - FEDER (B-TIC-624-UGR20)Consejo Superior de Investigaciones Científicas (CSIC) (project 20225AT012)Ramón y Cajal (grant RYC2020-030150-I

Variability and power enhancement of current controlled resistive switching devices

characterized using both current and voltage sweeps, with the device resistance and its cycle-to-cycle variability being analysed in each case. Experimental measurements indicate a clear improvement on resistance states stability when using current sweeps to induce both set and reset processes. Moreover, it has been found that using current to induce these transitions is more efficient than using voltage sweeps, as seen when analysing the device power consumption. The same results are obtained for devices with a Ni top electrode and a bilayer or pentalayer of HfO2/Al2O3 as dielectric. Finally, kinetic Monte Carlo and compact modelling simulation studies are performed to shed light on the experimental resultsConsejería de Conocimiento, Investigaci´on y Universidad, Junta de Andalucía (Spain)FEDER program for the project B-TIC-624-UGR20Spanish Consejo Superior de Investigaciones Científicas (CSIC) for the intramural project 20225AT012Ramón y Cajal grant No. RYC2020-030150-I

On the VCO/Frequency Divider Interface in Cryogenic CMOS PLL for Quantum Computing Applications

The availability of quantum microprocessors is mandatory, to efficiently run those quantum al-gorithms promising a radical leap forward in computation capability. Silicon-based nanostruc-tured qubits appear today as a very interesting approach, because of their higher information density, longer coherence times, fast operation gates, and compatibility with the actual CMOS technology. In particular, thanks to their phase noise properties, the actual CMOS RFIC Phase-Locked Loops (PLL) and Phase-Locked Oscillators (PLO) are interesting circuits to synthe-size control signals for spintronic qubits. In a quantum microprocessor, these circuits should op-erate close to the qubits, that is, at cryogenic temperatures. The lack of commercial cryogenic Design Kits (DK) may make the interface between the Voltage Controlled Oscillator (VCO) and the Frequency Divider (FD) a serious issue. Nevertheless, currently this issue has not been sys-tematically addressed in the literature. The aim of the present paper is to investigate the VCO/FD interface when the temperature drops from room to cryogenic. To this purpose, physi-cal models of electronics passive/active devices and equivalent circuits of VCO and the FD were developed at room and cryogenic temperatures. The modeling activity has led to design guide-lines for the VCO/FD interface, useful in the absence of cryogenic DKs

Characterization and optimization of network traffic in cortical simulation

Considering the great variety of obstacles the Exascale systems have to face in the next future, a deeper attention will be given in this thesis to the interconnect and the power consumption. The data movement challenge involves the whole hierarchical organization of components in HPC systems — i.e. registers, cache, memory, disks. Running scientific applications needs to provide the most effective methods of data transport among the levels of hierarchy. On current petaflop systems, memory access at all the levels is the limiting factor in almost all applications. This drives the requirement for an interconnect achieving adequate rates of data transfer, or throughput, and reducing time delays, or latency, between the levels. Power consumption is identified as the largest hardware research challenge. The annual power cost to operate the system would be above 2.5 B$ per year for an Exascale system using current technology. The research for alternative power-efficient computing device is mandatory for the procurement of the future HPC systems. In this thesis, a preliminary approach will be offered to the critical process of co-design. Co-desing is defined as the simultaneos design of both hardware and software, to implement a desired function. This process both integrates all components of the Exascale initiative and illuminates the trade-offs that must be made within this complex undertaking

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Daily Eastern News: March 01, 2004

https://thekeep.eiu.edu/den_2004_mar/1000/thumbnail.jp

Daily Eastern News: March 01, 2004

https://thekeep.eiu.edu/den_2004_mar/1000/thumbnail.jp