High-Voltage Devices in Smart Power Technology

Tato práce se zabývá popisem základních vlastností LDMOS tranzistorů. V první části práce jsou rozebrány vlastnosti LDMOS tranzistorů, jejich základní parametry a techniky pro vylepšení parametrů těchto tranzistorů. V další části je rozebrána spolehlivost LDMOS tranzistorů, tato část popisuje bezpečnou pracovní oblast (SOA), injekci horkých nosičů (HCI) a negativní teplotní stabilitu (NBTI). Poslední teoretická část popisuje používané modely pro simulaci ESD událostí. Praktická část práce je zaměřena na simulaci základních parametrů PLDMOS a NLDMOS tranzistorů, porovnání simulovaných a změřených koncentračních profilů. Dále se práce zabývá simulacemi změny geometrických parametrů PLDMOS tranzistoru a vliv těchto změn na elektrické parametry. Poslední část práce tvoří TLP simulace, které zkoumají elektrické vlastnosti PLDMOS tranzistoru při použití jako ESD ochrana.This work describes fundamental characteristics of LDMOS transistors. In the first part of work are described properties of LDMOS transistors, the basic parameters and techniques to improve parameters of transistors. The next section discusses the reliability of LDMOS transistors. This section describes the safe operating area (SOA), hot carrier injection (HCI) and negative bias temperature instability (NBTI). The last theoretical section describes models used to simulate ESD events. The practical part is focused on simulation of the basic parameters PLDMOS and NLDMOS transistors and comparison of simulated and measured concentration profiles. Furthermore the thesis deals with simulation of the impact of changes in geometrical parameters of the PLDMOS transistor and the impact of these changes on the electrical parameters. The last part contains TLP simulations which examines electrical properties of PLDMOS transistor when is used as ESD protection.

Hot-Carrier Degradation in Power LDMOS: Selective LOCOS-Versus STI-Based Architecture

In this paper, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOS (LDMOS) transistors. Two architectures with the same nominal voltage and comparable performance featuring a selective LOCOS and a shallow-trench isolation are investigated by means of constant voltage stress measurements and TCAD simulations. In particular, the on-resistance degradation in linear regime is experimentally extracted and numerically reproduced under different stress conditions. A similar amount of degradation has been reached by the two architectures, although different physical mechanisms contribute to the creation of the interface states. By using a recently developed physics-based degradation model, it has been possible to distinguish the damage due to collisions of single high-energetic electrons (single-particle events) and the contribution of colder electrons impinging on the silicon/oxide interface (multiple-particle events). A clear dominance of the single-electron collisions has been found in the case of LOCOS structure, whereas the multiple-particle effect plays a clear role in STI-based device at larger gate-voltage stress

Influence of material quality and process-induced defects on semiconductor device performance and yield

An overview of major causes of device yield degradation is presented. The relationships of device types to critical processes and typical defects are discussed, and the influence of the defect on device yield and performance is demonstrated. Various defect characterization techniques are described and applied. A correlation of device failure, defect type, and cause of defect is presented in tabular form with accompanying illustrations

Electrical characterization and modelling of lateral DMOS transistor:investigation of capacitances and hot-carrier impact

With the work reported in this manuscript we have essentially contributed to the electrical characterization and modelling of high voltage MOSFETs, more particularly DMOS architectures such as X-DMOS and L-DMOS able to sustain voltages ranging from 30V to 100V. The technology information and the investigated devices have been kindly provided by AMIS, Belgium (former Alcatel Microelectronics). In general, all the initial defined targets in term of the orientation of our work, as defined in the introduction chapter, have been maintained along the progress of the work. However, sometimes, based on the obtained results we have decided to pay more attention to some less explored topics such as the hot carrier impact of DMOS capacitances and the combined effect of stress and temperature, which initially were not among the planned activities. However, we believe that we have contributed to some of the planned targets. We experimentally validated the concept of intrinsic drain voltage; a modeling concept dedicated to the modeling of HV MOSFET and demonstrated its usefulness for the DC and AC modelling of HV devices. We proposed an original mathematical yet quasi-empirical formulation for the bias-dependent drift series resistance of DMOS transistor, which is very accurate for modelling all the regimes of operation of the high voltage device. We combined for the first time such a model with EKV low voltage MOSFET model developed at EPFL. We also have reported on models for the capacitances of high voltage devices at two levels: equivalent circuits for small signal operation based on VK-concept and large signal charge-based models. These models capture the main physical charge distribution in the device but they are less adapted for fast circuit simulation. In the field of device reliability, we have originally contributed to the investigation of hot carrier effects on DC and AC characteristics of DMOS transistors, with key emphasis on the degradation of transistor capacitances and the influence of the temperature. At our knowledge, our work reported in this chapter is among the first reports existing in this field. We have essentially shown that the monitoring of capacitance degradation if mandatory for a deep understanding of the degradation mechanisms and, in conjunction with DC parameter degradation, could offer correct insights for reliability issues. Even more, we have shown situations (by comparing two fundamental types of stresses) when the capacitance degradation method by HC is much more sensitive than DC parameter degradation method. Of course, some of the combined stress-temperature investigations were too complex to find very coherent explications for all the observed effects but our work stress out the interest and significance of such an approach for defining the SOA of high voltage devices, in general. Overall, our work can be considered as placed at the interface between electrical characterization and modelling of high voltage devices emerging from conventional low voltage CMOS technology, continuing the research tradition in the field established at the Electronics laboratory (LEG) of EPF Lausanne

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric