Self-checking multiple-valued circuit based on dual-rail current-mode differential logic

科研費報告書収録論文(課題番号:09558027・基盤研究(B)(2)・H9～H12/研究代表者:羽生, 貴弘/1トランジスタセル多値連想メモリの試作とその応用

Challenge of a multiple-valued technology in recent deep-submicron VLSI

科研費報告書収録論文(課題番号:13558026・基盤研究(B)(2)・13～16/研究代表者:羽生, 貴弘/転送ボトルネックフリー多値ロジックインメモリVLSIの開発と応用

Exploration and Design of High Performance Variation Tolerant On-Chip Interconnects

Siirretty Doriast

Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy consumption, less noise and EMI emission, and easy design reuse are some of the benefits of these circuits. NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms that has been shown to be a promising method for designing delay-insensitive asynchronous circuits. This dissertation investigates new areas in NCL design and test and is made of three sections. The first section discusses different CMOS implementations of NCL gates and proposes new circuit techniques to enhance their operation. The second section focuses on mapping multi-rail logic expressions to a standard NCL gate library, which is a form of technology mapping for a category of NCL design automation flows. Finally, the last section proposes design for testability techniques for a recently developed low-power variant of NCL called Sleep Convention Logic (SCL)

Exploitation of Unintentional Information Leakage from Integrated Circuits

Unintentional electromagnetic emissions are used to recognize or verify the identity of a unique integrated circuit (IC) based on fabrication process-induced variations in a manner analogous to biometric human identification. The effectiveness of the technique is demonstrated through an extensive empirical study, with results presented indicating correct device identification success rates of greater than 99:5%, and average verification equal error rates (EERs) of less than 0:05% for 40 near-identical devices. The proposed approach is suitable for security applications involving commodity commercial ICs, with substantial cost and scalability advantages over existing approaches. A systematic leakage mapping methodology is also proposed to comprehensively assess the information leakage of arbitrary block cipher implementations, and to quantitatively bound an arbitrary implementation\u27s resistance to the general class of differential side channel analysis techniques. The framework is demonstrated using the well-known Hamming Weight and Hamming Distance leakage models, and approach\u27s effectiveness is demonstrated through the empirical assessment of two typical unprotected implementations of the Advanced Encryption Standard. The assessment results are empirically validated against correlation-based differential power and electromagnetic analysis attacks

Mixed radix design flow for security applications

The purpose of secure devices, such as smartcards, is to protect sensitive information against software and hardware attacks. Implementation of the appropriate protection techniques often implies non-standard methods that are not supported by the conventional design tools. In the recent decade the designers of secure devices have been working hard on customising the workflow. The presented research aims at collecting the up-to-date experiences in this area and create a generic approach to the secure design flow that can be used as guidance by engineers. Well-known countermeasures to hardware attacks imply the use of specific signal encodings. Therefore, multi-valued logic has been considered as a primary aspect of the secure design. The choice of radix is crucial for multi-valued logic synthesis. Practical examples reveal that it is not always possible to find the optimal radix when taking into account actual physical parameters of multi-valued operations. In other words, each radix has its advantages and disadvantages. Our proposal is to synthesise logic in different radices, so it could benefit from their combination. With respect to the design opportunities of the existing tools and the possibilities of developing new tools that would fill the gaps in the flow, two distinct design approaches have been formed: conversion driven design and pre-synthesis. The conversion driven design approach takes the outputs of mature and time-proven electronic design automation (EDA) synthesis tools to generate mixed radix datapath circuits in an endeavour to investigate the added relative advantages or disadvantages. An algorithm underpinning the approach is presented and formally described together with secure gate-level implementations. The obtained results are reported showing an increase in power consumption, thus giving further motivation for the second approach. The pre-synthesis approach is aimed at improving the efficiency by using multivalued logic synthesis techniques to produce an abstract component-level circuit before mapping it into technology libary. Reed-Muller expansions over Galois field arithmetic have been chosen as a theoretical foundation for this approach. In order to enable the combination of radices at the mathematical level, the multi-valued Reed-Muller expansions have been developed into mixed radix Reed-Muller expansions. The goals of the work is to estimate the potential of the new approach and to analyse its impact on circuit parameters down to the level of physical gates. The benchmark results show the approach extends the search space for optimisation and provides information on how the implemented functions are related to different radices. The theory of two-level radix models and corresponding computation methods are the primary theoretical contribution. It has been implemented in RMMixed tool and interfaced to the standard EDA tools to form a complete security-aware design flow.EThOS - Electronic Theses Online ServiceEPSRCGBUnited Kingdo

Side-channel attacks and countermeasures in the design of secure IC's devices for cryptographic applications

Abstract--- A lot of devices which are daily used have to guarantee the retention of sensible data. Sensible data are ciphered by a secure key by which only the key holder can get the data. For this reason, to protect the cipher key against possible attacks becomes a main issue. The research activities in hardware cryptography are involved in finding new countermeasures against various attack scenarios and, in the same time, in studying new attack methodologies. During the PhD, three different logic families to counteract Power Analysis were presented and a novel class of attacks was studied. Moreover, two different activities related to Random Numbers Generators have been addressed

Master of Science

thesisFully integrated, implantable, and wireless neural interface systems typically re-quire a forward data link in addition to the telemetry link that transmits data from the chip. One popular way to create this forward data link is to amplitude modulate the magnetic fi eld of the inductive link that provides the device with wireless power. However, the limitations of these channels when loaded with a recti fier and amplitude modulated have not previously been characterized, and this lack of understanding caused previous versions of the Integrated Neural Interface (INI) to have forward data communication issues, which needed to be corrected for the next generation of the device, INIR8. This thesis first develops an analytical method of characterizing this sort of wireless channel. It then shows measurement data that verifies the validity of the model in the desired region of operation. The available bandwidth as determined by this analytical method, and confirmed by simulation, is insufficient for many applications. Therefore, the next subject of this thesis is to increase the data rate beyond what the bandwidth of the system can intrinsically support by using an equalization technique. This technique is shown to support very robust data recovery under a variety of operating conditions and to data rates much higher than otherwise possible. Another way to improve the reliability of data recovery is to develop a robust digital control system with error detection capabilities. This was done for INIR8, and works very reliably. The end result of this eff ort is a very robust forward data communication in INIR8, as well as a new analytical method for characterizing inductively coupled channels with certain loads and modulation techniques

High Temperature Electronics Design for Aero Engine Controls and Health Monitoring

There is a growing desire to install electronic power and control systems in high temperature harsh environments to improve the accuracy of critical measurements, reduce the amount of cabling and to eliminate cooling systems. Typical target applications include electronics for energy exploration, power generation and control systems. Technical topics presented in this book include:• High temperature electronics market• High temperature devices, materials and assembly processes• Design, manufacture and testing of multi-sensor data acquisition system for aero-engine control• Future applications for high temperature electronicsHigh Temperature Electronics Design for Aero Engine Controls and Health Monitoring contains details of state of the art design and manufacture of electronics targeted towards a high temperature aero-engine application. High Temperature Electronics Design for Aero Engine Controls and Health Monitoring is ideal for design, manufacturing and test personnel in the aerospace and other harsh environment industries as well as academic staff and master/research students in electronics engineering, materials science and aerospace engineering