科研費報告書収録論文(課題番号:13558026・基盤研究(B)(2)・13～16/研究代表者:羽生, 貴弘/転送ボトルネックフリー多値ロジックインメモリVLSIの開発と応用

Hanyu Takahiro

Hanyu, Takahiro

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Challenge of a multiple-valued technology in recent deep-submicron VLSI

application/pdf学術論文 (Article)科研費報告書収録論文(課題番号:13558026・基盤研究(B)(2)・13～16/研究代表者:羽生, 貴弘/転送ボトルネックフリー多値ロジックインメモリVLSIの開発と応用)487978 bytesjournal articl

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Challenge of a Mult iple-Valued Technology in Recent Deep-Submicron VLSI Takahiro Hanyu Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University Aoba-yama 05, Sendai 980-8579, Japan Phone : +81-22-217-7153 Fax : +81-22-263-9401 E-mail : hanyu@kameyama. ecei. tohoku .ac .jp Abstract A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass- transistor logic is proposed to  solve a com- munication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitabe for self-checking and asyn- chronous VLSI systems. Finally, the advan- tage of the above multiple-valued circuit tech- nologies is shown by using design examples. 1. Introduction Communication bottleneck between mem- ory and logic modules is one of the most seri- ous problems in recent deep submicron VLSI systems, especially in the multimedia VLSI systems on a single chip [1],[2]. A logic-in- memory structure, in which storage functions are distributed over a logic-circuit plane, is a key technology to solve the above problem [3] ,141. However, the logic-in-memory VLSI ar- chitecture may be generally more complex to build than a normal one where a logic-circuit plane is separated from a memory module, be- cause of the overhead involved in the storage and logic elements. Moreover, an asynchronous-control tech- nique and a fault-tolerance technique as well as high-performance system architectures and circuit design techniques, have become in- creasingly important in recent deep submi- cron VLSI chips. The self-checking circuit, that is an important fault-tolerance technique, has the capability to test for the occurrence of transient and permanent faults within the circuit by a normal input, as well as to de- tect errors a t  the input itself [5],[6]. And, the asynchronous-cnntro! circuit technique is a key to solve a clock-distribution problem due to interconnection complexity in the re- cent deep-submicron VLSI chips. However, the use of the present binary CMOS gates re- quires large number of transistors for realiz- ing self-checking and asynchronous-control cir- cuits [7]-[9]. This paper presents some multiple-valued (MV) circuit technologies to  realize a high- performance or a highly reliable VLSI proces- sor in the recent deep-submicron chip. First, a logic-in-memory VLSI using floating-gate- MOS pass-transistor logic [lo]-[12] is proposed to merge storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit. Multiple-valued stored data are represented by the thresh- old voltage of a floating-gate MOS transistor 1131, so that both multiple-valued threshold- literal and pass-switch functions [14],[15] can be merged by using a single floating-gate MOS transistor. In addition, a new multiple-valued current- mode (MVCM) circuit based on dual-rail dif- ferential logic is proposed to realize both a totally self-checking circuit [16] and an asynchronous-control circuit [ 171 with keeping a high-driving capability a t  a low supply volt- age. 241 0-7695-1083-3/01 $ 0.00 0 2001 IEEE Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on December 14, 2009 at 00:24 from IEEE Xplore.  Restrictions apply. Digit line Digit line Match line Match line Threshold Word line (GND) Floating gate Figure 1 : Multiple-valued CAM cell structure. 2 .  MV circuit technol- ogy for logic-in-memory VLSI architecture Nonvolatile devices such as floating-gate MOS transistors and ferroelectric devices are generally used as memory cell devices [MI- [19]. Since a nonvolatile device can be uti- lized not only as a memory element but also as a switching one, a circuit design using non- volatile devices has a potential advantage to realize a high-performance VLSI system with less communication bottleneck between stor- age and logic elements [20]-[22]. -4s a typical example, Figure 1 shows a multiple-valued CAM cell circuit where a multiple-valued threshold function and a pass- switch function are merged into a multiple- valued storage element by a single floating- gate MOS transistor. Using the principle of the above circuit structure, Figure 2 shows a layout of a highly parallel collision-detection VLSI processor for intelligent vehicles un- der a 0.8-pm CMOS technology. I t  includes two kinds of components: a multiple-valued CAM and eight processing elements (PES) for high-speed coordinate transformations. Fre- quent communication between the PES and the CAM is required for collision detection, so that they must be integrated on a single chip. 3 .  MV circuit technol- ogy for self checking and asynchronous control It has been known that data representa- tion based on dual-rail coding is useful as a code word in self-checking and asynchronous- control circuits. Since an MVCM circuit based on dual-rail differential logic has a potential advantage to realize a high-speed logic circuit at a low supply voltage, the MVCM circuit - ---11.7 (rnm) : I  ................. ............... Figure 2: Layout of a collision-detection VLSI processor with a 4-valued CAM. Figure 3: Totally self-checking circuit based on dual-rail MVCM differntial logic. technology is compatible with the realization of self-checking and asynchronous-control cir- cuits. Figure 3 shows a chip photomicrogragh of a totally self-checking MVCM circuit. A non-self-checking (NSC) differential-pair cir- cuit (DPC) is proposed and has a redundant function because one of the dual-rail outputs depends on only a single input in the NSC DPC. Accordingly, a self-checking DPC can be designed by the duplication of the proposed NSC DPC. As a result, a self-checking MVCM circuit can be easily designed by using the pro- posed NSC DPCs in replacement of the origi- nal NSC DPC, while other basic components such as comparators and wired-sum circuits still remain used to  realize the self-checking circuit. 242 Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on December 14, 2009 at 00:24 from IEEE Xplore.  Restrictions apply. Figure 4: Asynchronous-control circuit .based on dual-rail MVCM differntial logic. Figure 4 show a chip photomicrograph of an MVCM circuit for asynchronous-control VLSi system. In the proposed two-color asyn- chronous communication, a four-valued data value is represented by a pair of seven-valued dual-rail complementary digits. In odd and even phases, the sums of dual-rail digit pairs becomes ’3’ and ’9’, respectively. There- fore, the use of this dual-rail coding makes it easy to detect three different states such as an odd-phase data-arrival state, an even- phase data-arrival state and a data-transition state in the two-color asynchronous commu- nication. Moreover, the two-color dual-rail four-valued coding can be easily extended to any multiple-valued data representation. In the viewpoint of compact asynchronous cir- cuit realization, the MVCM circuit technique is suitable because the signal-state detection for asynchronous data transfer is performed by using the sum of dual-rail digit pairs and its threshold operation whose basic operations are compactly realized by using the dual-rail MVCM circuit techniques. 4 .  Conclusion Some multiple-valued circuit technologies have been introduced and their usefulness and easiness for chip fabrication are shown by us- ing concrete examples. -4s a future prospect of the proposed multiple-valued circuit technolo- gies, it is also important to combine voltage- mode circuit technologies into current-mode Figure 5: MV hybrid-mode circuit for 4-valued full addition with a 4-valued storage element. ones, called a “hybrid-mode” circuit technol- ogy [23]. A multiple-valued current-mode logic circuit is suited to  implement arithmetic VLSI systems. For example, Figure 5 shows a hybrid-mode multiple-valued circuit for th. use of the hybrid-mode circuit technology will have a possibility to enhance the performance of muletiple-valued VLSI systems more and more in the recent deep-submicron era. Acknowledgment The author wishes to thank Michitaka Kameyama of Tohoku University for many helpful comments. References [l] J.  Borel, “Technologies for Multimedia Systems on a Chip,” Digest of Tech- nical Papers, IEEE International Solid- State Circuits Conference, TA1.l, pp.18- 21, Feb., 1997. [2] H. Veendrick, “Deep-Submicron CMOS ICs,” Kluwer Bedrijfshformatie, 1998. [3] W. H. Kautz, “Cellular Logic-in-Memory -4rrays,” IEEE Trans. on Computer, Vo1.C-18, No.8, pp.719-727, Aug., 1969. [4] D. G .  Elliott et al., “Computational R-4A4: Implemeting Processors in Mem- ory,” IEEE Design & Test of Computers, pp. 32-4 1, Jan .-M arch, 1999. [5] D. A. Anderson and G. Metze, “Design of totally self-checking check circuits for m- out-of-n codes,” IEEE Trans. Computers, v0l.C-22, no.3, pp.263-269, Mar. 1973. 243 Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on December 14, 2009 at 00:24 from IEEE Xplore.  Restrictions apply. [6] J.  F. Wakerly, Error Detecting Codes: Self- Checking Circuits and Applications, Elsevier North-Holland, New York, 1978. Based on Dual-Rail Current-hllode Differ- entia1 Logic,” IEEE International Sympo- sium on Multiple-Valued Logic, pp.275- 279, May 1999. [7] ,4. K. Goel, High-speed VLSI Intercon- nections, Wiley Interscience, 1994. [8] G. Birtwistle and A. Davis, Asgnchronous Digital Circuit Design, Springer, 1995. [9] M. Afghahi and C. Svensson, “Perfor- mance of synchronous and asynchronous scheme for VLSI systems,” IEEE Trans. Computers, vo1.41, No.7, pp.858-872, July 1992. M. Kameyama, “Design of a One- Transistor-Cell Multiple-valued CAM,” IEEE Journal of Solid-state Circuits, Vol. [lo] T. Hanyu, N. Kanagawa and SC-31, NO. 11, pp.1669-1674, NOV. 1996. [ll] T. Hanyu, K. Teranishi and M. Kameyama, “Multiple-Valued logic- in-Memory VLSI Based on a Floating- gate-MOS Pass- Transistor Network” IEEE International Solid-state Circuits Conference, F P  12.5, pp. 194-195, Feb. 1998. [12] T. Hanyu and M. Kameyama, “Multiple- Valued Logic-in-Memory VLSI Architec- ture Based on Floating-Gate-MOS Pass- Transistor Logic” IEICE Trans. Electron- ics, Vol.E82-C, No.9, pp. 1662-1668, Sep. 1999. [13] T. Higuchi and M. Kameyama, “Multiple-Valued Digital Processing Sys- tem,” Shokodo Co. Ltd., Tokyo, 1989 (in Japanese). [14] D. Radhakrishnan, S. R. Whitaker and G. K. Maki, “Formal Design Procedures for Pass Transistor Switching Circuits” IEEE Journal of Solid-state Circuits, VolSC- 20, No.2, pp.531-536, April 1985. [15] -4. Parameswar, H. Hara and T. Sakurai, ”.4 High Speed, Low Power, Swing Re- stored Pass-Transistor Logic Based Mul- tiply and Accumulate Circuit for Mul- timedia Applications,” IEEE 1994 Cus- tom Integrated Circuits Conf., pp.278- 281, May 1994. [17] T .  Hanyu, T. Ike and M.  Kameyama, “Integration of Asynchronous and Self- Checking h4ultiple-Valued Circuits Based on Dual-Rail Differential Logic,” IEEE 2000 Pacific Rim International Sympo- sium on Dependable Computing, pp.27- 33. Dec. 2000. [18] C. Hu, “Nonvolatile Semiconductor Mem- ories Technologies, Design and Applica- tions” IEEE PRESS, 1991. [19] W. D. Brown and J .  E. Brewer, “Non- volatile Semiconductor Memory Technol- ogy, A Comprehensive Guide to Un- derstanding and Using NVSM Devices” IEEE PRESS, 1997. [20] T. Miwa, “A 1Mh 2-Transistor/bit Non- Volatile CAM Based on Flash-Memory Technologies,” Digest of Technical Pa- pers, IEEE International Solid-state Cir- cuits Conference, TP2.5, pp.40-41, Feb., 1996. [21] .4. Sheikholeslami, P. G. Gulak and T. Hanyu, “A Multiple-valued Ferroelectric Content-Addressable Memory,” IEEE International Symposium on Multiple- Valued Logic, pp.74-79, May 1996. [22] T. Hanyu, H. Kimura and M. Kameyama, “Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric- Semiconductor FETs,” IEEE Interna- tional Symposium on Multiple-valued Logic, pp.30-35, May 1999. [23] T. Hanyu, S. Kaeriyama and M. Kameyama, “Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic” IEEE International Symposium on Multiple-valued Logic, pp. 438-443, May 2000. [16] T. Hanyu, T. Ike and M. Kameyama, “Self-checking Multiple-valued Circuit 244 Authorized licensed use limited to: TOHOKU UNIVERSITY. Downloaded on December 14, 2009 at 00:24 from IEEE Xplore.  Restrictions apply. 

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Challenge of a multiple-valued technology in recent deep-submicron VLSI

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