Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V

Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations

A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternat-ing U-shaped n/p– SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resis-tance. The folded U-shaped n/p– pillar uniformly distributes the electric field in the SJ drift region.The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of different carrier transport models are carried out with different doping profiles by calibrating the drift-diffusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and specific on-resistance (Ron,sp). The effect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the fixed ratio between the pillar width and the pillar height.It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-off ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V , thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device offers a specific on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the specific on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of offering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum specific on-resistance, and excellent FoM for sub - 100 V rating applications.Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Different scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping profile is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low specific on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V . Additionally, the scaled SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V , respectively.Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, specific on-resistance, and physical density for a higher integration in a CMOS architecture

Scaling and optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub–50 V applications

The scaling of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 50 V) requires a subsequent optimisation of SJ unit. The scaling and the SJ optimisation are carried out with physically based commercial TCAD device simulations by Silvaco. The study is based on a meticulous calibration of drift-diffusion simulations against experimental characteristics of a 1 μm gate length SJ multi-gate MOSFET (SJ-MGFET) aiming at improving density, switching speed, drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate scaling of the device architecture to improve the device performance by optimising doping profile to achieve an avalanche-enabled device under a charge balanced condition. The optimised SJ-MGFETs scaled by a factor of 0.5 and 0.25, with a folded alternating U-shaped n/p-SJ drift region pillar of a width of 0.3 μm and a trench depth of 2.7 μm, achieve a low specific on-resistance (Ron,sp) of 7.68 mΩ⋅mm2 and 2.24 mΩ⋅mm2 (VGS = 10 V) and BV of 48 V and 26 V, respectively. The scaled 0.5 μm and 0.25 μm gate length SJ-MGFETs offer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V, respectively, greatly improving the levels of integration in a CMOS architecture

Simulation of superjunction MOSFET devices

Master'sMASTER OF ENGINEERIN

Physics and technologies of silicon LDMOSFET for radio frequency applications

This thesis is devoted to the investigation of devices and technologies of Lateral Double-Diffused- Metal-Oxide-Semiconductor-Field-Effect-Transistor for Radio Frequency (RP) applications. Theoretical analysis and extensive 2-D process and device simulation results are presented. Theoretical analysis and simulations are carried out on RESURF LDMOS in both bulk and SOI substrate in terms of breakdown characteristics, transconductance, on resistance and CV characteristics. Quasi-saturation is a common phenomenon in DMOS devices. In this work, the dependence of quasi-saturation current on device physical and geometrical parameters is investigated in SOI RP LDMOS. Physical insight is gained into quasi-saturation on SOI RP LDMOS with different top silicon thickness and the same drift dose. It reveals that the difference in thick and thin film SOI lies in the different potential drop in the drift region. The influence of RESURF effect on quasi-saturation is also presented. It is shown that quasi-saturation current level can be affected by RESURF due to its influence on the drift dose. The mechanism of self-heating is presented and the influence of top silicon thickness, buried oxide thickness, voltage bias is studied through simulations. The change of peak temperature and its location with bias is due to the shift of electric field with voltage bias. A back-etch structure and fabrication process have been proposed to achieve a superior thermal performance. The negative differential conductance is not present in the non-isothermal IV curves. The temperature rise in the back-etch structure is less than 114 of that in the bulk structure. An RP LDMOS with a step drift doping profile on SIMOX substrate is evaluated. The fabrication process for the drift formation is proposed. The presented results demonstrate that step drift device has higher breakdown voltage than the conventional uniformly doped (UD) device, which provides the possibility to integrate LDMOS with low voltage CMOS for 28V base station application. This structure also has the advantage of suppressed kink effect due to the reduced electric field within the drift region. The step drift structure also features lower capacitance, improved drain current saturation behaviour and reduced self-heating at class AB bias point. For the first time, a novel sandwich structure for lateral RF MOSFET has been analysed based on silicon-on-nothing (SON) technology. The influence of device parameters on BV, CV and thermal performance has been investigated. Partial SON structure is found preferable in terms of heat conduct ability. Comparison on the electrical and thermal performance is made between SON LDMOSFET and conventional SOI alternative with BV of 40V. It is found that SON structure shows improvement in output capacitance and substrate loss. However, the temperature rise in SON device is higher compared to SOI alternative. The performance of the proposed sandwich SON structure has also been investigated in 28V base station applications, which requires breakdown voltage of 80V

A Resonant One-Step 325 v to 3.3-10 v DC-DC Converter with Integrated Power Stage Benefiting from High-Voltage Loss-Reduction Techniques

This work presents a self-timed resonant high-voltage (HV) dc-dc converter in HV CMOS silicon-on-insulator (SOI) with a one-step conversion from 100-325 V input down to a 3.3-10 V output, optimized for applications below 500 mW, such as IoT, smart home, and e-mobility. Unlike bulky power modules, the HV converter is fully integrated, including an on-chip power stage, with only one external inductor (10 $\mu \text{H}$ ) and capacitor (470 nF). It reaches a high power density of 752 mW/cm3, an overall peak efficiency as high as 81%, and a light-load efficiency of 73.2% at 5 V and 50 mW output. HV loss-reduction techniques are presented and experimentally confirmed to offer an efficiency improvement of more than 32%. Integrated HV insulated gate bipolar transistors (IGBTs) are discussed and implemented as an attractive alternative to conventional integrated HV power switches, resulting in 20% smaller area at lower losses

Three-Dimensional Simulation Study of Low Voltage (\u3c100V) Superjunction Lateral DMOS power transistors

A new revolutionary concept was presented two decades ago, known as semiconductor Superjunction (SJ) theory to enhance the trade-off relationship between specific on resistance, Rsp, and off-state breakdown voltage, BV, in medium to high voltages (more than 100 V) power MOSFETs. The SJ concept was first applied and commercialized to vertical structures, but it hasn\u27t been used yet in low voltage MOSFETs with lateral structures. This thesis provides a review of the most common structures, principles and design techniques for discrete power MOSFETs. It also presents a simulation study of the application of these SJ concepts in the design of a Low Voltage SJ LDMOS transistor, using TCAD software. To make the device commercially feasible, this device design targets aggressive goals such as an off-state Breakdown Voltage of 60V with Rsp of 20 miliohms per milimiter square. This study includes the analysis of the flow process for the fabrication of this transistor, using semiconductor technologies, and the simulation results, including Breakdown Voltage, on-state resistance, electric field distribution among others simulation analysis

High voltage 3-dimesional partial SOI technology platform for power integrated circuits

Partial SOI (PSOI) is a widely recognized technology suitable for High Voltage (HV) architectures for Power Integrated Circuits (PICs). Despite the added process complexity compared to SOI RESURF, this technology offers a wider range of voltage ratings due to the action of the depletion layer in the Handle Wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-dimensional designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low on-state resistance and reduced selfheating are essential requirements. This work presents a PSOI technology platform with voltage ratings ranging from 45 to 400V while providing low on-state resistance, good hot carrier injection stability as well as Electrostatic Discharge (ESD) capability of the HV devices. For example, for a 375V rated LDMOSFET, this technology achieves an on-state resistance of 1435mΩ.mm2 , an over 50% improvement compared to the state-of-the-art SOI technologies while maintaining competitive reliability

Oxide bypassed power MOSFET devices

Master'sMASTER OF ENGINEERIN

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric