Power efficient and high performance VLSI architecture for AES algorithm

AbstractAdvanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay

Analysis of New L5 Algorithm Embedded with Modified AES Algorithm in Address Allocation Schemes

Networking is ubiquitous. In this fast-moving world, routing plays a major role for a myriad of purposes in the internet space. Address allocation is a vital component in routing. It is very much important to route the packets securely to the preferred destination. The routing of packets is not as efficient as it should have been. The current routing process is tedious and time consuming. The vulnerabilities found in the AES algorithm have been exploited by hackers and sniffers. In order to overcome these backlogs, two new mathematically validated approaches, namely, new L5 routing algorithm and modifiedAES algorithm are proposed in this article. The proposed schemes circumscribe the possibilities of hacking. The mathematical exploration of the proposed schemes results in reduced time and space complexities. The newly proposed routing algorithm achieves fault tolerance, secure transmission of data and provides congestion contro

Study of Data Security Algorithms using Verilog HDL

This paper describes an overview of data security algorithms and its performance evaluation. AES, RC5 and SHA algorithms have been taken under this study. Three different types of security algorithms used to analyze the performance study. The designs were implemented in Quartus-II software. The results obtained for encryption and decryption procedures show a significant improvement on the performance of the three algorithms. In this paper, 128-bit AES, 64-bit of RC5 and 512-bit of SHA256 encryption and Decryption has been made using Verilog Hardware Description Language and simulated using ModelSim

Barrel Shifter Physical Unclonable Function Based Encryption

Physical Unclonable Functions (PUFs) are circuits designed to extract physical randomness from the underlying circuit. This randomness depends on the manufacturing process. It differs for each device enabling chip-level authentication and key generation applications. We present a protocol utilizing a PUF for secure data transmission. Parties each have a PUF used for encryption and decryption; this is facilitated by constraining the PUF to be commutative. This framework is evaluated with a primitive permutation network - a barrel shifter. Physical randomness is derived from the delay of different shift paths. Barrel shifter (BS) PUF captures the delay of different shift paths. This delay is entangled with message bits before they are sent across an insecure channel. BS-PUF is implemented using transmission gates; their characteristics ensure same-chip reproducibility, a necessary property of PUFs. Post-layout simulations of a common centroid layout 8-level barrel shifter in 0.13 {\mu}m technology assess uniqueness, stability and randomness properties. BS-PUFs pass all selected NIST statistical randomness tests. Stability similar to Ring Oscillator (RO) PUFs under environment variation is shown. Logistic regression of 100,000 plaintext-ciphertext pairs (PCPs) failed to successfully model BS- PUF behavior

Enhanced secure data transfer for WSN using chaotic-based encryption

Postupci na bežičnim senzorskim mrežama - Wireless Sensor Networks (WSN) i njihovim područjima uporabe sve su češći pa problem sigurnosti mreže postaje sve važniji. Budući da su snaga procesora, memorija i izvori energije ograničeni na čvorove bežičnih senzorskih mreža, tradicionalno strukturirani kodovi više nisu učinkoviti. Uzevši to u obzir, očita je potreba za manjim procesnim opterećenjem i potrošnjom energije te učinkovitim kodom. U ovom se radu razvija kaotični kodni sustav za zadovoljenje sigurnosnih potreba na WSN. Uspoređuju se ovdje razvijeni kaotični sustav i uobičajeno korišteni Skipjack kod uz pomoć algoritma OPNET Modeller softvera i konstatira se da su postignuti bolji rezultati.Processes on Wireless Sensor Networks (WSN) and their areas of use have become more widespread, and the issue of net-work security has appeared as one of the primary necessities. As power of the processor, memory and energy sources are limited on wireless sensor network nodes, traditional encryption structures are not found effective. With these criteria taken into consideration, the need for less process load and energy consumption as well as a powerful encryption is obvious. In this study, a chaotic encryption system to meet the security need on WSN using chaotic systems was carried out. The chaotic system developed here and the commonly used Skipjack encryption were compared with the help of algorithm OPNET Modeller software and better results were achieved

A low cost advance encryption standard (AES) co-processor implementation

The need for privacy has become a major priority for both governments and civilians desiring protection from signal interception. Widespread use of personal communications devices has only increased demand for a level of security on previously insecure communications. This paper presents a novel low-cost architecture for the Advanced Encryption Standard (AES) algorithm utilizing a field programmable gate array (FPGA). In as much as possible, this architecture uses a bit-serial approach, and it is also suitable for VLSI implementations. In this implementation, the primary objective was not to increase throughput or decrease latency, but to balance these factors in order to lower the cost. A focus on low cost resulted in a design well-suited for SoC implementations. This allows for scaling of the architecture towards vulnerable portable and cost-sensitive communications devices in consumer and military applications.Facultad de Informátic

The hardware implementation of a high performance AES based on inner pipeline

为了提升AES的性能,本文采用轮内流水线技术进行AES硬件设计。在对AES轮单元复杂的字节代换/逆字节代换、列变换/逆列变换进行了算法分析的基础上,进行了AES轮单元的轮内7级流水线设计。特别是采用常数矩阵乘积形式和复用列变换进行了逆列变换设计,降低了硬件资源的占用。采用XIlInX ISE10.1工具进行了各个型号fPgA的硬件实现,实验数据表明文中提出的硬件实现方案提升了AES的数据吞吐率与吞吐率/面积比。Abtract: An inner pipelined hardware design of AES is presented in this paper for the performance improvement of AES.Based on the algorithmic analysis of the SubBytes/invSubBytes and MixColumns/invMixColumns, a 7-stage pipelined structure, which applies the invMixColumns design to the multiplexing MixColumns and adopts the form of arithmetic product of constant matrix, is proposed to reduce the cost of the hardware resources.The implementation of the proposed is carried out in several FPGAs using the Xilinx ISE10.1and the results have shown an improvement in thedatathroughoutratioand theratioofdatathroughoutand area

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

VLSI implementation of AES algorithm

In the present era of information processing through computers and access of private information over the internet like bank account information even the transaction of money, business deal through video conferencing, encryption of the messages in various forms has become inevitable. There are mainly two types of encryption algorithms, private key (also called symmetric key having single key for encryption and decryption) and public key (separate key for encryption and decryption). In the present work, hardware optimization for AES architecture has been done in different stages. The hardware comparison results show that as AES architecture has critical path delay of 9.78 ns when conventional s-box is used, whereas it has critical path delay of 8.17 ns using proposed s-box architecture. The total clock cycles required to encrypt 128 bits of data using proposed AES architecture are 86 and therefore, throughput of the AES design in Spartan-6 of Xilinx FPGA is approximately 182.2 Mbits/s. To achieve the very high speed, full custom design of s-box in composite field has been done for the proposed s-box architecture in Cadence Virtuoso. The novel XOR gate is proposed for use in s-box design which is efficient in terms of delay and power along with high noise margin. The implementation has been done in 180 nm UMC technology. Total dynamic power in the proposed XOR gate is 0.63 µW as compared to 5.27 µW in the existing design of XOR. The designed s-box using proposed XOR occupies a total area of 27348 µm2. The s-box chip consumes 22.6 µW dynamic power and has 8.2 ns delay after post layout simulation has been performed