A robust high-efficiency cross-coupled charge pump circuit without blocking transistors

This document is the Accepted Manuscript version of the following article: Minglin Ma, Xinglong Cai, Yichuang Sun, and Nike George, ‘A robust high-efficiency cross-coupled charge pump circuit without blocking transistors’, Analog Integrated Circuits and Signal Processing, Vol. 95 (3): 395-401, June 2018. Under embargo until 16 March 2019. The final publication is available at Springer via: https://doi.org/10.1007/s10470-018-1149-xA fully integrated cross-coupled charge pump circuit with a new clock scheme has been presented in this paper. The new clock scheme ensures that all NMOS pre-charge transistors are turned off when the voltages of main clock signals are high. Notably, all PMOS transfer transistors will be turned off when the voltages of the main clock signals are low. As a result, the charge pump eliminates all of the reversion power loss and reduces the ripple voltage. The proposed charge pump has a better performance even in scenarios where the main clock signals are mismatched. The proposed charge pump circuit was simulated using spectre in the TSMC 0.18 µm CMOS process. The simulation results show that the proposed charge pump circuit has a high voltage conversion efficiency and low ripple voltage.Peer reviewe

Circuit Modules for CMOS High-Power Short Pulse Generators

High-power short electrical pulses are important for high-performance functionality integration, such as the development of microelectromechanical/nanoelectromechanical systems (MEMS/NEMS), system on chip (SoC) and lab on chip (LoC). Many of these applications need high-power (low impedance load) short electrical pulses, in addition to CMOS digital intelligence. Therefore, it is of great interest to develop new circuit techniques to generate high-power high-voltage short electrical pulses on-chip. Results on pulse forming line (PFL) based CMOS pulse generator studies are reported. Through simulations, the effects of PFL length, switch speed and switch resistance on the output pulses are clarified. CMOS pulse generators are modeled and analyzed with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In the 0.13 um CMOS process with a 500 um long PFL, post layout simulations show that pulses of 10.4 ps width can be obtained. High-voltage and high-power outputs can be generated with other pulsed power circuits, such as Blumlein PFLs with stacked MOSFET switches. Thus, the PFL circuit significantly extends short and high-power pulse generation capabilities of CMOS technologies. A CMOS circuit with a 4 mm long PFL is implemented in the commercial 0.13 um technology. Pulses of ~ 160 ps duration and 110-200 mV amplitude on a 50 Ohms load are obtained when the power supply is tuned from 1.2 V to 2.0 V. Measurement Instruments limitations are probably the main reasons for the discrepancies among measurement and simulation results. A four-stage charge pump is presented as high voltage bias of the Blumlein PFLs pulse generator. Since Schottky diode has low forward drop voltage (~ 0.3V), using it as charge transfer cell can have high charge pumping gain and avoid additional control circuit for switch. A four-stage charge pump with Schottky diode as charge transfer cell is implemented in a commercial 0.13 um technology. Charge pump output and efficiency under different power supply voltages, load currents and clock frequencies are measured and presented. The maximum output voltage is ~ 6 V and the maximum efficiency is ~ 50%

High-efficiency high voltage hybrid charge pump design with an improved chip area

A hybrid charge pump was developed in a 0.13- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage

Monolithic Integration of CMOS Charge Pumps for High Voltage Generation beyond 100 V

Monolithic integration of step-up DC-DC converters used to be one of the largest challenges in high voltage CMOS SoCs. Charge pumps are considered as the most promising solution regarding in- tegration levels compared to boost converter with bulky inductors. However, conventional charge pump architectures usually show significant drawbacks and reliability problems, when used as on- chip high voltage generators. Hence, innovative charge pump architectures are required to realize the monolithic integration of charge pumps in high voltage applications. In this dissertation, three 4-phase charge pump architectures with the dynamic body biasing tech- nique and clock schemes with dead time techniques were proposed to overcome drawbacks such as body effect and reverse current problem of traditional Pelliconi charge pump. The influences of high voltage CMOS sandwich capacitors on the voltage gain and power efficiency of charge pumps were extensively investigated. The most reasonable 4-phase charge pump architecture with a suitable configuration of high voltage sandwich capacitors regarding the voltage gain and power efficiency was chosen to implement two high voltage ASICs in an advanced 120 V 0.35 μm high voltage CMOS technology. The first test chip operates successfully and is able to generate up to 120 V from a 3.7 V low voltage DC supply, which shows the highest output voltage among all the reported fully integrated CMOS charge pumps. The measurement results confirmed the benefits of the proposed charge pump architectures and clock schemes. The second chip providing a similar output voltage has a reduced chip size mainly due to decreased capacitor areas by increased clock frequencies. Fur- thermore, the second chip with an on-chip clock generator works independently of external clock signals which shows the feasibility of integrated charge pumps as part of high voltage SoCs. Based on the successful implementation of those high voltage CMOS ASICs, further discussions on the stability of the output voltage, levels of integration and limitations in the negative high voltage generation of high voltage CMOS charge pumps are held with the aid of simulation or measurement results. Feed- back regulation by adjusting the clock frequency or DC power supply is able to stabilize the voltage performance effectively while being easily integrated on-chip. Increasing the clock frequency can significantly reduce the required capacitor values which results in reduced chip sizes. An application example demonstrates the importance of fully integrated high voltage charge pumps. Besides, a new design methodology for the on-chip high voltage generation using CMOS technolo- gies was proposed. It contains a general design flow focusing mainly on the feasibility and reliability of high voltage CMOS ASICs and design techniques for on-chip high voltage generators. In this dissertation, it is proven that CMOS charge pumps using suitable architectures regarding the required chip size and circuit reliability are able to be used as on-chip high voltage generators for voltages beyond 100 V . Several methods to improve the circuit performance and to extend the functionalities of high voltage charge pumps are suggested for future works

A Charge Pump Architecture with High Power-Efficiency and Low Output Ripple Noise in 0.5 μm CMOS Process Technology

The demand of portable consumer electronic devices is skyrocketing day-by-day. Such modern integrated microsystems have several functional blocks which require different voltages to operate adequately. DC-DC converter circuits are used to generate different voltage domains for different functional blocks on large integrated microsystems from a single voltage battery-operated power supply. Charge pump is an inductorless DC-DC converter which generates higher positive voltage or lower voltage or negative voltage from the applied reference voltage. A charge pump circuit uses switches for charge transfer action and capacitors for charge storage. The thesis presents a high power-efficiency charge pump architecture with low output ripple noise in the AMI N-well 0.5 µm CMOS process technology. The switching action of the proposed charge pump architecture is controlled by a dual phase non-overlapping clock system. In order to achieve high power-efficiency, the power losses due to the leakage currents, the finite switch resistance and the imperfect charge transfer between the capacitors are taken into consideration and are minimized by proper switching of the charge transfer switches and by using different auxiliary circuits. To achieve low output ripple noise, the continuous current pumping method is proposed and implemented in the charge pump architecture. The proposed charge pump can operate over the wide input voltage range varying from 3 V to 7 V with the power conversion efficiency of 90%. The loading current drive capability of the proposed charge pump is ranging from 0 to 45 mA. The worst case output ripple voltage is less than 25 mV. To prove the concept, the design of the proposed charge pump is simulated rigorously over different process, temperature and voltage corners

High Efficiency Cross-Coupled Charge Pump Circuit with Four-Clock Signals

© Allerton Press, Inc. 2018A fully integrated cross-coupled charge pump circuit for boosting dc-to-dc converter applications with four-clock signals has been proposed. With the new clock scheme, this charge pump eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the power supply voltage for solving the gate-oxide overstress problem in the conventional charge pump circuits and enhancing the reliability. This proposed charge pump circuit does not require any extra level shifter; therefore, the power efficiency is increased. The proposed charge pump circuit has been simulated using Spectre in the TSMC 0.18 μm CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5Vis 99.8%. According to the comparison results of the conventional pump and the enhanced charge pump proposed, the output ripple voltage has been significantly reduced.Peer reviewe

A High Efficiency and Low Ripple Cross-Coupled Charge Pump Circuit

A fully integrated cross-coupled charge pump circuit with four-clock signals and a new method of body bias have been proposed. The new clock scheme eliminates all of the reversion power loss and reduces the ripple voltage. In addition, the largest voltage differences between the terminals of all transistors do not exceed the supply voltage. We have also solved the gate-oxide overstress problem in the conventional charge pump circuits and enhanced the reliability. The proposed charge pump circuit has been simulated using Spectre and in the TSMC 0.18um CMOS process. The simulation results show that the maximum voltage conversion efficiency of the new 3-stage cross-coupled circuit with an input voltage of 1.5V is 99.8%. Moreover, the output ripple voltage has been significantly reduced.Peer reviewe

A high-efficiency and compact charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. The proposed four-stage charge pump with finger capacitor can achieve 14.2 V output voltage from a 3 V power supply. The finger capacitor can increase the power efficiency of the charge pump to 60.5% and save chip area as well

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump (design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc.) that are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were find based on the construct of the time response characteristics of the pump sub-block and finding of the maximal voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc. Synthesis process includes the design of the pump functional blocks with dominant real properties, which are described based on BSIM equations for long channel MOSFET. The pump stage complex model is applicated for estimation of the number of pump stages via state-space model description and using of the interpolation polynomial functions in the algorithm. It involves the construction of the time response characteristic due to the state variables and prediction of the number of the pump stages for the next cycle based on the previous data. Optimization of the pump area is based on the minimizing of the main capacitor in each of the pump stages (number of the pump stages must be increased to obtain the desired output voltage value.) Access is designed to stress the maximum pump voltage efficiency. The whole procedure is summarized in the practical example, in which the solution is shown both in terms of maximal voltage efficiency and the optimal pump area on a chip with respect to the clock signal frequency. Added functions of the design environment are explained, inclusive of the designed pump netlist generating for professional design environment Mentor Graphics including the real models of components that are available in library MGC Design Kit. The procedure gives designer credible results without long timeconsuming optimization process. In addition, the complex model allows the inclusion effects of higher-levels

New Analysis and Design of a RF Rectifier for RFID and Implantable Devices

New design and optimization of charge pump rectifiers using diode-connected MOS transistors is presented in this paper. An analysis of the output voltage and Power Conversion Efficiency (PCE) is given to guide and evaluate the new design. A novel diode-connected MOS transistor for UHF rectifiers is presented and optimized, and a high efficiency N-stage charge pump rectifier based on this new diode-connected MOS transistor is designed and fabricated in a SMIC 0.18-μm 2P3M CMOS embedded EEPROM process. The new diode achieves 315 mV turn-on voltage and 415 nA reverse saturation leakage current. Compared with the traditional rectifier, the one based on the proposed diode-connected MOS has higher PCE, higher output voltage and smaller ripple coefficient. When the RF input is a 900-MHz sinusoid signal with the power ranging from −15 dBm to −4 dBm, PCEs of the charge pump rectifier with only 3-stage are more than 30%, and the maximum output voltage is 5.5 V, and its ripple coefficients are less than 1%. Therefore, the rectifier is especially suitableto passive UHF RFID tag IC and implantable devices