Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Analysis and design of wideband voltage controlled oscillators using self-oscillating active inductors.

Voltage controlled oscillators (VCOs) are essential components of RF circuits used in transmitters and receivers as sources of carrier waves with variable frequencies. This, together with a rapid development of microelectronic circuits, led to an extensive research on integrated implementations of the oscillator circuits. One of the known approaches to oscillator design employs resonators with active inductors electronic circuits simulating the behavior of passive inductors using only transistors and capacitors. Such resonators occupy only a fraction of the silicon area necessary for a passive inductor, and thus allow to use chip area more eectively. The downsides of the active inductor approach include: power consumption and noise introduced by transistors. This thesis presents a new approach to active inductor oscillator design using selfoscillating active inductor circuits. The instability necessary to start oscillations is provided by the use of a passive RC network rather than a power consuming external circuit employed in the standard oscillator approach. As a result, total power consumption of the oscillator is improved. Although, some of the active inductors with RC circuits has been reported in the literature, there has been no attempt to utilise this technique in wideband voltage controlled oscillator design. For this reason, the dissertation presents a thorough investigation of self-oscillating active inductor circuits, providing a new set of design rules and related trade-os. This includes: a complete small signal model of the oscillator, sensitivity analysis, large signal behavior of the circuit and phase noise model. The presented theory is conrmed by extensive simulations of wideband CMOS VCO circuit for various temperatures and process variations. The obtained results prove that active inductor oscillator performance is obtained without the use of standard active compensation circuits. Finally, the concept of self-oscillating active inductor has been employed to simple and fast OOK (On-Off Keying) transmitter showing energy eciency comparable to the state of the art implementations reported in the literature

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Active inductor techniques for BW extension

Today nano-meter technologies benefit from higher integration allowing for increased complexity, but also higher speeds. Demand for higher speeds at lower area and cost system pushes toward more self-contained circuits without the use of integrated passive components due to the large area required. This work aims to take advantage of CMOS technology and its reduced cost to research and design active inductors and its integration in circuits. There are many circuits such as LNA, CTLE, CML buffers, voltage mode driver that may require passive inductors to enhance its performance in today's era demand for speed. A study of the different topologies/techniques will be performed with the respective evaluation of their pros and cons. Based on these, a circuit architecture will be proposed and developed integrated within a block circuit with proper validation of the circuit performance parameters like power, ageing, precision, reliability and other relevant parameters

RF-CMOS Switched-Capacitor Power Amplifier for NB-IoT RF transceivers

The increasing market of Narrowband Internet of Things (NB-IoT) applications brings new challenges and constrains in the design of fully integrated transmission architectures, capable of delivering the desired output power with the highest efficiency and linearity, ensuring the longest battery lifetime of the devices. This work is focused on the study and implementation of the most power consuming block within the transmission chain: the Power Amplifier (PA). In this regard, a Switched Capacitor Power Amplifier (SCPA) is designed to operate at a frequency of 0.9 GHz and aiming the maximum output power allowed by the standard of 23 dBm. The final architecture includes a matching network that connects to eight unit PA cells through an LC filter. Each unit PA cell is made of a cascoded class-D PA, two drivers, a level shifter and two selection logic blocks. All the blocks were developed using RF components from a UMC 130nm CMOS process with a 1.2V/2.4V supply voltage. The results show that the architecture is able to produce a maximum output power of 15.61 dBm with a maximum Power Added Efficiency (PAE) of 26.52% and a Total Harmonic Distortion (THD) of 0.68%. In the same conditions, the measured HD2 and HD3 are of -70.23dBc and -43.41dBc, respectively. Additionally, a modulation stage was implemented in VerilogA in order to evaluate the impact of sending different symbols in the SCPA performance. The block, designed for a 16 QAM modulation, is responsible for generating both the number of unit PA cells to be selected and the phase of the clock connected to each PA cell, depending on the amplitude and phase of the constellation points being transmitted.O mercado crescente de aplicações IoT de largura de banda estreita coloca novos desafios e restrições no desenvolvimento de arquiteturas de transmissão totalmente integradas, capazes de produzir a potência desejada com o máximo de eficiência e linearidade possí- veis, de forma a garantir o maior tempo de vida de bateria dos dispositivos. Este trabalho foca-se no estudo e implementação do bloco da cadeia de transmissão que mais consome: o amplificador de potência. Neste sentido, um amplificador de potência de condensadores comutados é desenhado para operar à frequência de 0.9GHz com o objetivo de produzir à sua saída o valor de potência máxima permitida pelo standard de 23dBm. A arquitetura inclui uma malha de adaptação que liga a oito PAs unitários através de um filtro LC. Cada PA unitário consiste num amplificador de potencia class-D cascoded, dois drivers, um level shifter e dois blocos de lógica de seleção. Todos estes blocos foram desenvolvidos usando componentes RF da tecnologia CMOS 130nm da UMC com uma tensão de alimentação de 1.2V/2.4V. Os resultados mostram que a arquitetura é capaz de produzir uma potência à saída de 15.61dBm, com uma PAE de 26.52% e uma distorção harmónica total de 0.68%. Nas mesmas condições, os valores medidos da HD2 e HD3 são de -70.23dBc e -43.41dBc, respetivamente. Adicionalmente, um andar de modulação foi implementado em VerilogA, de forma a avaliar o impacto de enviar diferentes símbolos na performance do amplificador. Este bloco, desenvolvido para uma modulacao 16QAM, é responsável por gerar o número de unidades de PA a serem selecionados e o relógio de fase que liga a cada PA unitário, dependendo da amplitude e fase dos pontos da constelação a serem transmitidos

All-Pass Sections with High Gain Opportunity

In this paper, two new circuits for realizing firstorder voltage-mode (VM) all-pass section (APS) with variable gain are presented. The first proposed filter uses a single differential difference current conveyor (DDCC), one grounded capacitor and three resistors. The second proposed filter consists of two DDCCs, three grounded resistors and one grounded capacitor. It provides highinput and low-output impedances and can provide high gain. Both of the proposed circuits do not require any element matching condition. Moreover, oscillator circuits with minimum number of active and passive elements are derived from the proposed APSs. The proposed circuits are tested experimentally or by simulation using SPICE program to confirm the theory

SiGe BiCMOS front-end circuits for X-Band phased arrays

The current Transmit/Receive (T/R) modules have typically been implemented using GaAs- and InP-based discrete monolithic microwave integrated circuits (MMIC) to meet the high performance requirement of the present X-Band phased arrays. However their cost, size, weight, power consumption and complexity restrict phased array technology only to certain military and satellite applications which can tolerate these limitations. Therefore, next generation X-Band phased array radar systems aim to use low cost, silicon-based fully integrated T/R modules. For this purpose, this thesis explores the design of T/R module front-end building blocks based on new approaches and techniques which can pave the way for implementation of fully integrated X-Band phased arrays in low-cost SiGe BiCMOS process. The design of a series-shunt CMOS T/R switch with the highest IP1dB, compared to other reported works in the literature is presented. The design focuses on the techniques, primarily, to achieve higher power handling capability (IP1dB), along with higher isolation and better insertion loss of the T/R switch. Also, a new T/R switch was implemented using shunt NMOS transistors and slow-wave quarter wavelength transmission lines. It presents the utilization of slow-wave transmissions lines in T/R switches for the first time in any BiCMOS technology to the date. A fully integrated DC to 20 GHz SPDT switch based on series-shunt topology was demonstrated. The resistive body oating and on-chip impedance transformation networks (ITN) were used to improve power handling of the switch. An X-Band high performance low noise ampli er (LNA) was implemented in 0.25 μm SiGe BiCMOS process. The LNA consists of inductively degenerated two cascode stages with high speed SiGe HBT devices to achieve low noise gure (NF), high gain and good matching at the input and output, simultaneously. The performance parameters of the LNA collectively constitute the best Figure-of-Merit value reported in similar technologies, to the best of author's knowledge. Furthermore, a switched LNA was implemented SiGe BiCMOS process for the first time at X-Band. The resistive body floating technique was incorporated in switched LNA design, for the first time, to improve the linearity of the circuit further in bypass mode. Finally, a complete T/R module with a state-of-the-art performance was implemented using the individually designed blocks. The simulations results of the T/R module is presented in the dissertation. The state-of-the-art performances of the presented building blocks and the complete module are attributed to the unique design methodologies and techniques

A Downconversion Beamforming RF Front-End in 130 nm CMOS technology

Due to the exponential growth of wireless data communications an increasing number of components compete for space in the frequency spectrum. Nowadays, different approaches have been addressed in order to overcome this problem. One of these approaches is using spatial filters instead of time-domain ones. Since most wireless devices operate by transferring/receiving signals to/from all directions, interfering signals are becoming an increasing problem. Thus steering the transmission/reception of signals in a specific direction alleviates this problem, which is performed by employing multiple antennas. In the scope of the spatial filtering approach, a 1 GHz downconvertion 4-element phased array receiver front-end is presented in this thesis, implemented in 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. The phase shifting of the beamforming receiver is implemented with a switched-capacitor vector modulator, that excels in its linearity and low power consumption. This receiver also provides a spatial rejection of more than 20 dB and good input matching