Scalable VLSI design for fast GF (p) montgomery inverse computation

This paper accelerates a scalable GF(p) Montgomery inversion hardware. The hardware is made of two parts a memory and a computing unit. We modified the original memory unit to include parallel shifting of all bits which was a task handled by the computing unit. The new hardware modeling, simulating, and synthesizing is performed through VHDL for several 160-bits designs showing interesting speedup to the inverse computation.British council in Saudi Arabia, KFUPM, Electrical & Computer Engineering Department of Brunel University in Uxbridg

Differential electromagnetic attack on an FPGA implementation of elliptic curve cryptosystems

This paper describes a differential electromagnetic analysis attack performed on a hardware implementation of an elliptic curve cryptosystem. We describe the use of the distance of mean test. The number of measurements needed to get a clear idea of the right guess of the key-bit is taken as indication of the success of the attack. We can find the right key-bit by using only 2000 measurements. Also we give a electromagnetic model for the FPGA we use in our experiments. The amplitude, the direction and the position of the current on the FPGA’s lines with respect to the position of the antenna have an influence on the measured electromagnetic radiation in the FPGA’s surrounding area

Fast 160-Bits GF (P) Elliptic Curve Crypto Hardware of High-Radix Scalable Multipliers

In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its data size to handle. The design adopts projective coordinates to eliminate most of the required GF(p) inversion calculations replacing them with several multiplication operations. The hardware is intended to be scalable, which allows the hardware to compute long precision numbers in a repetitive way. The design involves four parallel scalable multipliers to gain the best speed. This scalable design was implemented in different versions depending on the area and speed. All scalable implementations were compared with an available FPGA design. The proposed scalable hardware showed interesting results in both area and speed. It also showed some area-time flexibility to accommodate the variation needed by different crypto applications

Fast 160-Bits GF (P) Elliptic Curve Crypto Hardware of High-Radix Scalable Multipliers

In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its data size to handle. The design adopts projective coordinates to eliminate most of the required GF(p) inversion calculations replacing them with several multiplication operations. The hardware is intended to be scalable, which allows the hardware to compute long precision numbers in a repetitive way. The design involves four parallel scalable multipliers to gain the best speed. This scalable design was implemented in different versions depending on the area and speed. All scalable implementations were compared with an available FPGA design. The proposed scalable hardware showed interesting results in both area and speed. It also showed some area-time flexibility to accommodate the variation needed by different crypto applications

Efficient utilization of scalable multipliers in parallel to compute GF(p) elliptic curve cryptographic operations

This paper presents the design and implementation of an elliptic curve cryptographic core to realize point scalar multiplication operations used for the GF(p) elliptic curve encryption/decryption and the elliptic curve digital signature algorithm (ECDSA). The design makes use of projective coordinates together with scalable Montgomery multipliers for data size of up to 256-bits. We propose using four multiplier cores together with the ordinary projective coordinates which outperform implementations with Jacobean coordinates typically believed to perform better. The proposed architecture is particularly attractive for elliptic curve cryptosystems when hardware area optimization is the key concern

Estudio del diseño de un procesador criptográfico de Curvas Elípticas para el dispositivo WISP

El rápido avance del internet de las cosas ha supuesto plantear nuevas maneras de implementar las redes de sensores. Es así como la tecnología RFID se ha ido tornando cada vez más atractiva como una alternativa que no requiere el uso de baterías. La plataforma WISP (Wireless Identification Sensing Platform) es uno de los dispositivos que más ha permitido impulsar el desarrollo de sensores RFID. WISP es la primera etiqueta RFID computacional, es decir, que permite programar un algoritmo básico en su memoria. Sin embargo, al igual que con las redes de sensores actuales, estos dispositivos suelen ser blancos fáciles de atacantes cibernéticos ya que son un punto débil en la red debido a sus limitaciones en recursos de hardware y energía que dificultan desarrollar criptografías en software eficientes. En este trabajo se presenta un estudio sobre el diseño de una arquitectura para un procesador criptográfico de Curvas elípticas (ECC) de bajo consumo energético implementado que cumple con las limitaciones energéticas para ser utilizado con la etiqueta WISP. Este trabajo está basado en las arquitecturas propuestas por Ahmad Salman [1] y Siddika Berna [2].Trabajo de investigació

FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

The higher computational complexity of an elliptic curve scalar point multiplication operation limits its implementation on general purpose processors. Dedicated hardware architectures are essential to reduce the computational time, which results in a substantial increase in the performance of associated cryptographic protocols. This paper presents a unified architecture to compute modular addition, subtraction, and multiplication operations over a finite field of large prime characteristic GF(p). Subsequently, dual instances of the unified architecture are utilized in the design of high speed elliptic curve scalar multiplier architecture. The proposed architecture is synthesized and implemented on several different Xilinx FPGA platforms for different field sizes. The proposed design computes a 192-bit elliptic curve scalar multiplication in 2.3 ms on Virtex-4 FPGA platform. It is 34% faster and requires 40% fewer clock cycles for elliptic curve scalar multiplication and consumes considerable fewer FPGA slices as compared to the other existing designs. The proposed design is also resistant to the timing and simple power analysis (SPA) attacks; therefore it is a good choice in the construction of fast and secure elliptic curve based cryptographic protocols

Diseño de un procesador criptográfico de curvas elípticas para el dispositivo WISP

El internet de las cosas (IoT) está creciendo a un ritmo acelerado y con ello las redes de sensores están tomando una mayor importancia. Los nuevos avances se enfocan en disminuir los costos, facilitar la implementación y la escalabilidad de estas redes. En este sentido, la tecnología RFID es una alternativa que brinda mejoras en estos aspectos. Esto se debe a que al no usar baterías para la implementación de los nodos permite que sean más baratos y brinda más capacidad de conectividad. La plataforma WISP (Wireless Identification Sensing Platform) es una etiqueta RFID programable que facilita el desarrollo de nodos RFID y que ha facilitado la investigación de nuevos protocolos de comunicación y de seguridad en RFID. Por otro lado, un problema que afecta la adopción de esta tecnología es el gran incremento de ciberataques a nodos IoT en los últimos años. Esto se debe principalmente a su baja seguridad ya que con sus limitaciones en recursos de hardware y energía se dificulta desarrollar criptografías en software óptimas. En este trabajo se presenta la arquitectura de un procesador criptográfico de Curvas elípticas (ECC) de bajo consumo energético para un FPGA y que cumple con las limitaciones energéticas para ser utilizado con la etiqueta WISP. Además, el procesador propuesto soporta operaciones sobre GF(p) en curvas Weierstrass. Por otro lado, la operación de multiplicación modular se realiza utilizando el algoritmo Multiple Word Radix-2 Montgomery Multiplication (MWR2MM). De esta manera se puede implementar una arquitectura con forma de matriz sistólica lo que permite un alto nivel de paralelización y pipelining. Finalmente, se disminuyen las transiciones de señales y se eliminan los glitches que generan consumo energético innecesario. Se realizó la simulación utilizando un campo de 192 bits en el FPGA igloo AGL1000V2. Como resultado se obtuvo una latencia de 4,157,358 ciclos de reloj. Además, a una frecuencia de 6MHz se obtuvo una potencia de 5.74 mW lo cual implica que, a medio metro de distancia de la antena, la etiqueta WISP necesitará 1.6 segundos para completar una operación de multiplicación de punto

Hardware implementation of an elliptic curve processor over GF(p)

Contains fulltext : 127482.pdf (preprint version ) (Open Access)ASAP 2003 : 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors, June 24-26, The Hague, 200

Efficient implementation of elliptic curve cryptography.

Elliptic Curve Cryptosystems (ECC) were introduced in 1985 by Neal Koblitz and Victor Miller. Small key size made elliptic curve attractive for public key cryptosystem implementation. This thesis introduces solutions of efficient implementation of ECC in algorithmic level and in computation level. In algorithmic level, a fast parallel elliptic curve scalar multiplication algorithm based on a dual-processor hardware system is developed. The method has an average computation time of n3 Elliptic Curve Point Addition on an n-bit scalar. The improvement is n Elliptic Curve Point Doubling compared to conventional methods. When a proper coordinate system and binary representation for the scalar k is used the average execution time will be as low as n Elliptic Curve Point Doubling, which makes this method about two times faster than conventional single processor multipliers using the same coordinate system. In computation level, a high performance elliptic curve processor (ECP) architecture is presented. The processor uses parallelism in finite field calculation to achieve high speed execution of scalar multiplication algorithm. The architecture relies on compile-time detection rather than of run-time detection of parallelism which results in less hardware. Implemented on FPGA, the proposed processor operates at 66MHz in GF(2 167) and performs scalar multiplication in 100muSec, which is considerably faster than recent implementations.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .A57. Source: Masters Abstracts International, Volume: 44-03, page: 1446. Thesis (M.A.Sc.)--University of Windsor (Canada), 2005