Hardware Based Error and Flow Control in the Axon Gigabit Host-Network Interface

We have proposed a new architecture called Axon that meets the challenges of delivering high performance network bandwidth directly to applications. Its pipelines network interface must perform critical per packet processing in hardware a packets flow through the pipeline, without imposing any store-and-forward buffering of packets. This requires the design of error and flow control mechanisms to be simple enough for implementation in the network interface hardware, while providing functionality required by applications. This paper describes the implementation of the Axon host-network interface, and in particular the hardware design of the critical per packet processing with emphasis on error and flow control. An extensive simulation model of the network interface hardware has been used to determine the feasibility and performance of hardware implementation of these functions

The Axon Ethernet device

Data centers are growing in importance since computation is moving from personal computers to the Internet. Data centers often use Ethernet as the network fabric; however Ethernet presents fundamental limitations to scalability. This work examines the design, implementation, and characterization of the Axon, a network device that overcomes Ethernet's scalability limitations while maintaining the simplicity of such devices. Axons use cut-through routing to reduce the latency of communication and source-routing both to eliminate the spanning tree and to reduce state within the network. Using just one redundant link in small network has been shown to give a 96% increase to UDP bandwidth and a 63% increase to TCP bandwidth. Experiments confirm that an Axon's latency is an order of magnitude faster than that of a store-and-forward switch in an uncongested network, thereby increasing the potential diameter and improving the scalability of an Ethernet network

Scalable High-Speed Communications for Neuromorphic Systems

Field-programmable gate arrays (FPGA), application-specific integrated circuits (ASIC), and other chip/multi-chip level implementations can be used to implement Dynamic Adaptive Neural Network Arrays (DANNA). In some applications, DANNA interfaces with a traditional computing system to provide neural network configuration information, provide network input, process network outputs, and monitor the state of the network. The present host-to-DANNA network communication setup uses a Cypress USB 3.0 peripheral controller (FX3) to enable host-to-array communication over USB 3.0. This communications setup has to run commands in batches and does not have enough bandwidth to meet the maximum throughput requirements of the DANNA device, resulting in output packet loss. Also, the FX3 is unable to scale to support larger single-chip or multi-chip configurations. To alleviate communication limitations and to expand scalability, a new communications solution is presented which takes advantage of the GTX/GTH high-speed serial transceivers found on Xilinx FPGAs. A Xilinx VC707 evaluation kit is used to prototype the new communications board. The high-speed transceivers are used to communicate to the host computer via PCIe and to communicate to the DANNA arrays with the link layer protocol Aurora. The new communications board is able to outperform the FX3, reducing the latency in the communication and increasing the throughput of data. This new communications setup will be used to further DANNA research by allowing the DANNA arrays to scale to larger sizes and for multiple DANNA arrays to be connected to a single communication board

Diseño de una red de fibra óptica para el Mejoramiento de la distribución de servicios Integrados en el campamento trasvase olmos

La presente investigación se basó en el desarrollo de un diseño de red de comunicación basado en el medio de Fibra Óptica para la correcta realización de las actividades administrativas, de operación y mantenimiento de la Concesionaria Trasvase Olmos. Esta investigación comprende un desarrollo progresivo de diferentes etapas que inicia desde la recopilación bibliográfica y revisión de antecedentes hasta el procesamiento de los datos obtenidos, elaboración de arquitectura de red y análisis de los resultados que permiten la elaboración de una red de comunicación. Se planteó un diseño de red de fibra óptica mediante el análisis de la red de comunicaciones existente, lo cual se logró debido a visitas de campo al campamento Trasvase Olmos, toma de fotografías y recopilación de datos. A la vez se tomaron tests de velocidad de la red existente (cable UTP). El diseño de la red de comunicación de fibra óptica cumple con las especificaciones técnicas requeridas por la concesionaria Trasvase Olmos para le mejora de servicios de administración, operación y mantenimiento de la Presa Limón

SNAVA—A real-time multi-FPGA multi-model spiking neural network simulation architecture

© . This manuscript version is made available under the CC-BY-NC-ND 4.0 license http://creativecommons.org/licenses/by-nc-nd/4.0/Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.Peer ReviewedPostprint (author's final draft

Nanoresolution real-time 3D orbital tracking for studying mitochondrial trafficking in vertebrate axons in vivo

We present the development and in vivo application of a feedback-based tracking microscope to follow individual mitochondria in sensory neurons of zebrafish larvae with nanometer precision and millisecond temporal resolution. By combining various technical improvements, we tracked individual mitochondria with unprecedented spatiotemporal resolution over distances of >100 mu m. Using these nanoscopic trajectory data, we discriminated five motional states: a fast and a slow directional motion state in both the anterograde and retrograde directions and a stationary state. The transition pattern revealed that, after a pause, mitochondria predominantly persist in the original direction of travel, while transient changes of direction often exhibited longer pauses. Moreover, mitochondria in the vicinity of a second, stationary mitochondria displayed an increased probability to pause. The capability of following and optically manipulating a single organelle with high spatiotemporal resolution in a living organism offers a new approach to elucidating their function in its complete physiological context

Rapid Prototyping and Functional Verification of Power Efficient AI Processor on FPGA

Prototyping a design on a Field Programmable Gate Array (FPGA) involves different stages such as developing a design, performing synthesis, handling placement and routing and finally generating the programming bit file for the FPGA. After successful completion of the above stages, it is important to functionally verify the design. This thesis addresses the challenges involved in rapid prototyping and functional verification of a low power AI processor provided by the industry partner. This research also addresses the methodology used in generating programming bit file and testing the design. Traditional method of testing a design using RTL level testbench utilises more time and relies on functioning of other components associated with the design. This thesis incorporated a new technique of testing the design using software programs focusing on verification of the functionality of a particular module without depending on the other. This methodology reduced the time for functionality verification for part of the design from approximately 1 month to about 2 weeks. Finally, using the methodology mentioned above, the design was synthesized for two FPGA kits, along with analysing the power consumption of the design. The results show the low power nature of the design as it does not use any external memory resulting in faster Arithmetic Logic Unit (ALU) operations thereby saving time to access the data