Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology

In this paper, physical implementations and measurement results are presented for several Voltage Controlled Oscillators that were designed using a fully-automated, layout- and variability-aware optimization-based methodology. The methodology uses a highly accurate model, based on machine-learning techniques, to characterize inductors, and a multi-objective optimization algorithm to achieve a Pareto-optimal front containing optimal circuit designs offering different performance trade-offs. The final outcome of the proposed methodology is a set of design solutions (with their GDSII description available and ready-to-fabricate) that need no further designer intervention. Two key elements of the proposed methodology are the use of an optimization algorithm linked to an off-the-shelf simulator and an inductor model that yield EM-like accuracy but with much shorter evaluation times. Furthermore, the methodology guarantees the same high level of robustness against layout parasitics and variability that an expert designer would achieve with the verification tools at his/her disposal. The methodology is technology-independent and can be used for the design of radio frequency circuits. The results are validated with experimental measurements on a physical prototype

Una aproximación multinivel para el diseño sistemático de circuitos integrados de radiofrecuencia.

Tesis reducida por acuerdo de confidencialidad.En un mercado bien establecido como el de las telecomunicaciones, donde se está evolucionando hacia el 5G, se estima que hoy en día haya más de 2 Mil Millones de usuarios de Smartphones. Solo de por sí, este número es asombroso. Pero nada se compara a lo que va a pasar en un futuro muy próximo. El próximo boom tecnológico está directamente conectado con el mercado emergente del internet of things (IoT). Se estima que, en 2020, habrá 20 Mil Millones de dispositivos físicos conectados y comunicando entre sí, lo que equivale a 4 dispositivos físicos por cada persona del planeta. Debido a este boom tecnológico, van a surgir nuevas e interesantes oportunidades de inversión e investigación. De hecho, se estima que en 2020 se van a invertir cerca de 3 Mil Millones de dólares solo en este mercado, un 50% más que en 2017. Todos estos dispositivos IoT tienen que comunicarse inalámbricamente entre sí, algo en lo que los circuitos de radiofrecuencia (RF) son imprescindibles. El problema es que el diseño de circuitos RF en tecnologías nanométricas se está haciendo extraordinariamente difícil debido a su creciente complejidad. Este hecho, combinado con los críticos compromisos entre las prestaciones de estos circuitos, tales como el consumo de energía, el área de chip, la fiabilidad de los chips, etc., provocan una reducción en la productividad en su diseño, algo que supone un problema debido a las estrictas restricciones time-to-market de las empresas. Es posible concluir, por tanto, que uno de los ámbitos en los que es tremendamente importante centrarse hoy en día, es el desarrollo de nuevas metodologías de diseño de circuitos RF que permitan al diseñador obtener circuitos que cumplan con especificaciones muy exigentes en un tiempo razonable. Debido a las complejas relaciones entre prestaciones de los circuitos RF (por ejemplo, ruido de fase frente a consumo de potencia en un oscilador controlado por tensión), es fácil comprender que el diseño de circuitos RF es una tarea extremadamente complicada y debe ser soportada por herramientas de diseño asistido por ordenador (EDA). En un escenario ideal, los diseñadores tendrían una herramienta EDA que podría generar automáticamente un circuito integrado (IC), algo definido en la literatura como un compilador de silicio. Con esta herramienta ideal, el usuario sólo estipularía las especificaciones deseadas para su sistema y la herramienta generaría automáticamente el diseño del IC listo para fabricar (lo que se denomina diseño físico o layout). Sin embargo, para sistemas complejos tales como circuitos RF, dicha herramienta no existe. La tesis que se presenta, se centra exactamente en el desarrollo de nuevas metodologías de diseño capaces de mejorar el estado del arte y acortar la brecha de productividad existente en el diseño de circuitos RF. Por lo tanto, con el fin de establecer una nueva metodología de diseño para sistemas RF, se han de abordar distintos cuellos de botella del diseño RF con el fin de diseñar con éxito dichos circuitos. El diseño de circuitos RF ha seguido tradicionalmente una estrategia basada en ecuaciones analíticas derivadas específicamente para cada circuito y que exige una gran experiencia del diseñador. Esto significa que el diseñador plantea una estrategia para diseñar el circuito manualmente y, tras varias iteraciones, normalmente logra que el circuito cumpla con las especificaciones deseadas. No obstante, conseguir diseños con prestaciones óptimas puede ser muy difícil utilizando esta metodología, ya que el espacio de diseño (o búsqueda) es enorme (decenas de variables de diseño con cientos de combinaciones diferentes). Aunque el diseñador llegue a una solución que cumpla todas las especificaciones, nunca estará seguro de que el diseño al que ha llegado es el mejor (por ejemplo, el que consuma menos energía). Hoy en día, las técnicas basadas en optimización se están utilizando con el objetivo de ayudar al diseñador a encontrar automáticamente zonas óptimas de diseño. El uso de metodologías basadas en optimización intenta superar las limitaciones de metodologías previas mediante el uso de algoritmos que son capaces de realizar una amplia exploración del espacio de diseño para encontrar diseños de prestaciones óptimas. La filosofía de estas metodologías es que el diseñador elige las especificaciones del circuito, selecciona la topología y ejecuta una optimización que devuelve el valor de cada componente del circuito óptimo (por ejemplo, anchos y longitudes de los transistores) de forma automática. Además, mediante el uso de estos algoritmos, la exploración del espacio de diseño permite estudiar los distintos y complejos compromisos entre prestaciones de los circuitos de RF. Sin embargo, la problemática del diseño de RF es mucho más amplia que la selección del tamaño de cada componente. Con el objetivo de conseguir algo similar a un compilador de silicio para circuitos RF, la metodología desarrollada en la tesis, tiene que ser capaz de asegurar un diseño robusto que permita al diseñador tener éxito frente a medidas experimentales, y, además, las optimizaciones tienen que ser elaboradas en tiempos razonables para que se puedan cumplir las estrictas restricciones time-to-market de las empresas. Para conseguir esto, en esta tesis, hay cuatro aspectos clave que son abordados en la metodología: 1. Los inductores integrados todavía son un cuello de botella en circuitos RF. Los parásitos que aparecen a altas frecuencias hacen que las prestaciones de los inductores sean muy difíciles de modelar. Existe, por tanto, la necesidad de desarrollar nuevos modelos más precisos, pero también muy eficientes computacionalmente que puedan ser incluidos en metodologías que usen algoritmos de optimización. 2. Las variaciones de proceso son fenómenos que afectan mucho las tecnologías nanométricas, así que para obtener un diseño robusto es necesario tener en cuenta estas variaciones durante la optimización. 3. En las metodologías de diseño manual, los parásitos de layout normalmente no se tienen en cuenta en una primera fase de diseño. En ese sentido, cuando el diseñador pasa del diseño topológico al diseño físico, puede que su circuito deje de cumplir con las especificaciones. Estas consideraciones físicas del circuito deben ser tenidas en cuenta en las primeras etapas de diseño. Por lo tanto, con el fin de abordar este problema, la metodología desarrollada tiene que tener en cuenta los parásitos de la realización física desde una primera fase de optimización. 4. Una vez se ha desarrollado la capacidad de generar distintos circuitos RF de forma automática utilizando esta metodología (amplificadores de bajo ruido, osciladores controlados por tensión y mezcladores), en la tesis se aborda también la composición de un sistema RF con una aproximación multinivel, donde el proceso empieza por el diseño de los componentes pasivos y termina componiendo distintos circuitos, construyendo un sistema (por ejemplo, un receptor de radiofrecuencia). La tesis aborda los cuatro problemas descritos anteriormente con éxito, y ha avanzado considerablemente en el estado del arte de metodologías de diseño automáticas/sistemáticas para circuitos RF.Premio Extraordinario de Doctorado U

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

BiCMOS Millimetre-wave low-noise amplifier

Abstract: Please refer to full text to view abstract.D.Phil. (Electrical and Electronic Engineering

TERASENSE: THz device technology laboratory: final summary

The use of THz frequencies, particularly W and G band allows reaching higher resolution and deeper penetration in emerging applications like imaging, sensing, etc. The development of those new applications lays on reliable technologies, background of expertise and know-how. The CDS2008-00068 TERASENSE CONSOLIDER project has given the opportunity to extent upwards in frequency the previous background of the microwaves research group partners. This article summarizes the developments of the TERASENSE work package “THz Device Technology Laboratory”.This work was supported by the Spanish Ministerio de Ciencia e Innovación through the CONSOLIDER-INGENIO 2010 program reference CSD2008-00068 TERASENSE

Circuit Design

Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects

Methods and tools for the design of RFICs

Ambient intelligence is going to focus the next advances in wireless technologies. Hence, the increasing demand on radio frequency (RF) devices and applications represents, not only a challenge for technological industries to improve its roadmaps, but also for RF engineers to design more robust, low-power, small-size and low-cost devices. Regarding to communication robustness, in the latest years, differential topologies have acquired an important relevance because of its natural noise and interference immunity. Within this framework, a differential n-port device can still be treated with the classical analysis circuit theory by means of Z-,Y-, h-parameters or the most suitable S-parameters in the radio frequency field. Despite of it, Bockelman introduced the mixed-mode scattering parameters, which more properly express the differential and common-mode behavior of symmetrical devices. Since then, such parameters have been used with a varying degree of success, as it will be shown, mainly because of a misinterpretation. Thereby, this thesis is devoted to extend the theory of mixed-mode scattering parameters and proposes the methodology to analyze such devices. For this proposal, the simplest case of a two-port device is developed. By solving this simple case, most of the lacks of the current theory are filled up. As instance, it allows the characterization and comparison of symmetric and spiral inductors, which have remained a controversy point until now. After solving this case, the theory is extended to a n-port device. Another key point on the fast and inexpensive development of radio frequency devices is the advance on fast CAD tools for the analysis and synthesis of passive devices. In the case of silicon technologies, planar inductors have become the most popular shapes because of its integrability. However, the design of inductors entails a deep experience and acknowledge not only on the behavior of such devices but on the use of electromagnetic (EM) simulators. Unfortunately, the use of EM simulators consumes an important quantity of time and resources. Thereby, this thesis is devoted to improve some of the aspects that slow down the synthesis process of inductors. Therefore, an ‘ab initio’ technique for the meshing of planar radio frequency and microwave circuits is described. The technique presented can evaluate the losses in the component with a high accuracy just in few seconds where an electromagnetic simulator would normally last hours. Likewise, a simple bisection algorithm for the synthesis of compact planar inductors is presented. It is based on a set of heuristic rules obtained from the study of the electromagnetic behavior of these planar devices. Additionally, design of a single-ended to differential low noise amplifier (LNA) in a CMOS technology is performed by using the methods and tools described.L'enginyeria de radiofreqüència i la tecnologia de microones han assolit un desenvolupament inimaginable i avui en dia formen part de la majoria de les nostres activitats diàries. Probablement, la tecnologia mòbil ha tingut un desenvolupament més ràpid que qualsevol altre avenç tecnològic de l'era digital. Avui en dia, podem dir que el paradigma de la mobilitat s'ha assolit i tenim accés ràpid a internet des de qualsevol lloc on podem estar amb un dispositiu de butxaca. No obstant això, encara hi ha fites per endavant. Es més que probable que el paradigma de l’ "ambient intelligence” sigui el centre dels pròxims avenços en les tecnologies sense fils. A diferencia del paradigma de l"ambient intelligence', l'evolució de la tecnologia de la informació mai ha tingut l'objectiu explícit de canviar la societat, sinó que ho van fer com un efecte secundari, en canvi, les visions d' “ambient intelligence” proposen expressament el transformar la societat mitjançant la connexió completa i la seva informatització. Per tant, l'augment de la demanda de dispositius de ràdio freqüència (RF) i de les seves possibles aplicacions representa, no només un repte per a les indústries tecnològiques per millorar els seus plans de treball, sinó també per als enginyers de RF que hauran de dissenyar dispositius de baixa potència, més robusts, de mida petita i de baix cost. Quant a la robustesa dels dispositius, en els últims anys, les topologies de tipus diferencial han adquirit una important rellevància per la seva immunitat natural al soroll i resistència a les interferències. Dins d'aquest marc, un dispositiu de nports diferencial, encara pot ser tractat com un dispositiu 2nx2n i la teoria clàssica d'anàlisi de circuits (és a dir, la temia de quadripols) es pot aplicar a través de paràmetres Z, Y, h o els paràmetres S, més adequats en el camp de freqüència de ràdio. Tot i això, Bockelman i Eisenstadt introdueixen els paràmetres S mixtos, que expressen més adequadament el comportament diferencial i en mode comú de dispositius simètrics o asimètrics. Des de llavors, aquests paràmetres s'han utilitzat amb un grau variable d'èxit, com es mostrarà, principalment a causa d'una mala interpretació. D'aquesta manera, la primera part d'aquesta tesi està dedicada a estendre la teoria dels paràmetres S de mode mixt i proposa la metodologia d'anàlisi d'aquest tipus de dispositius i circuits. D'aquesta forma, en el Capítol 2, es desenvolupa el cas més simple d'un dispositiu de dos ports. En resoldre aquest cas simple, la major part de les mancances de la teoria actual es posen de relleu. Com a exemple, pennet la caracterització i la comparació de bobines simètriques i espiral no simètriques, que han estat un punt de controvèrsia fins ara. Després de resoldre aquest cas, al Capítol 3 s'estén la teOIia a un dispositiu de n-ports dels quals un nombre pot ser single-ended i la resta diferencials. És en aquest moment quan la dualitat existent entre els paràmetres S estàndard i de mode mixt es pot veure clarament i es destaca en el seu conjunt. Aquesta teoria permet, tanmateix, estendre la teoria clàssica d'amplificadors quan s'analitzen per mitjà de paràmetres S. Un altre punt clau en el desenvolupament ràpid i de baix cost dels dispositius de radiofreqüència és l'avenç en les eines CAD ràpides per a l'anàlisi i síntesi dels dispositius passius, en especial dels inductors. Aquests dispositius apareixen tot sovint en el disseny de radio freqüència degut a la seva gran versatilitat. Tot i que hi ha hagut múltiples intents de reemplaçar amb components externs o circuits, fins i tot actius, en el cas de les tecnologies de silici, els inductors planars s'han convertit en les formes més populars per la seva integrabilitat. No obstant això, el disseny d'inductors implica conèixer i posseir una experiència profunda no només en el comportament d'aquests dispositius, però també en l'ús de simuladors electromagnètics (EM). Desafortunadament, l'ús dels simuladors EM consumeix una quantitat important de temps i recursos. Per tant, la síntesi dels inductors representa un important inconvenient actualment. D'aquesta manera, la segona part d'aquesta tesi està dedicada a millorar alguns dels aspectes que frenen el procés de síntesi dels inductors. Per tant, en el Capítol 4, es descriu una tècnica 'ab initio' de generació de la malla per bobines planars en ràdio freqüència i microones. La tècnica es basa en l'estudi analític dels fenòmens d'aglomeració de corrent que tenen lloc a l'interior del component. En aquesta avaluació, no es requereix una solució explícita dels corrents i de les càrregues arreu del circuit. Llavors, el nombre de cel•les de la malla assignades a una tira de metall donada, depèn del valor inicialment obtingut a partir de l'estudi analític. La tècnica presentada pot avaluar les pèrdues en el component amb una gran precisió només en uns pocs segons, quan comparat amb un simulador electromagnètic normalment es necessitaria hores. De la mateixa manera, en el Capítol 5 es presenta un senzill algoritme de bisecció per a la síntesi d'inductors planars compactes. Es basa en un conjunt de regles heurístiques obtingut a partir de l'estudi del comportament electromagnètic d'aquests dispositius planars. D'aquesta manera, el nombre d'iteracions es manté moderadament baix.D'altra banda, per tal d'accelerar l'anàlisi en cada pas, s'utilitza un simulador ràpid electromagnètic planar, el qual es basa en el coneixement que es té del component sintetitzat. Finalment, en el Capítol 6, la metodologia de paràmetres S de mode mixt proposada i les eines CAD introduides s'utilitzen àmpliament en el disseny d'un amplificador de baix soroll “single-ended” a diferencial (LNA), mitjançant una tecnologia estàndard CMOS.L'amplificador de baix soroll és un dels components claus en un sistema de recepció de radio freqüència, ja que tendeix a dominar la sensibilitat i la figura de soroll (NF) de tot el sistema. D'altra banda, les característiques d'aquest circuit estan directament relacionades amb els components actius i passius disponibles en una tecnologia donada. Per tant, la tecnologia escollida, el factor de qualitat dels passius, i la forma com es caracteritzen tindran un alt impacte en les principals figures de mèrit del circuit real

Adaptive Suppression of Interfering Signals in Communication Systems

The growth in the number of wireless devices and applications underscores the need for characterizing and mitigating interference induced problems such as distortion and blocking. A typical interference scenario involves the detection of a small amplitude signal of interest (SOI) in the presence of a large amplitude interfering signal; it is desirable to attenuate the interfering signal while preserving the integrity of SOI and an appropriate dynamic range. If the frequency of the interfering signal varies or is unknown, an adaptive notch function must be applied in order to maintain adequate attenuation. This work explores the performance space of a phase cancellation technique used in implementing the desired notch function for communication systems in the 1-3 GHz frequency range. A system level model constructed with MATLAB and related simulation results assist in building the theoretical foundation for setting performance bounds on the implemented solution and deriving hardware specifications for the RF notch subsystem devices. Simulations and measurements are presented for a Low Noise Amplifer (LNA), voltage variable attenuators, bandpass filters and phase shifters. Ultimately, full system tests provide a measure of merit for this work as well as invaluable lessons learned. The emphasis of this project is the on-wafer LNA measurements, dependence of IC system performance on mismatches and overall system performance tests. Where possible, predictions are plotted alongside measured data. The reasonable match between the two validates system and component models and more than compensates for the painstaking modeling efforts. Most importantly, using the signal to interferer ratio (SIR) as a figure of merit, experimental results demonstrate up to 58 dB of SIR improvement. This number represents a remarkable advancement in interference rejection at RF or microwave frequencies

Circuit Design

Circuit Design = Science + Art! Designers need a skilled "gut feeling" about circuits and related analytical techniques, plus creativity, to solve all problems and to adhere to the specifications, the written and the unwritten ones. You must anticipate a large number of influences, like temperature effects, supply voltages changes, offset voltages, layout parasitics, and numerous kinds of technology variations to end up with a circuit that works. This is challenging for analog, custom-digital, mixed-signal or RF circuits, and often researching new design methods in relevant journals, conference proceedings and design tools unfortunately gives the impression that just a "wild bunch" of "advanced techniques" exist. On the other hand, state-of-the-art tools nowadays indeed offer a good cockpit to steer the design flow, which include clever statistical methods and optimization techniques.Actually, this almost presents a second breakthrough, like the introduction of circuit simulators 40 years ago! Users can now conveniently analyse all the problems (discover, quantify, verify), and even exploit them, for example for optimization purposes. Most designers are caught up on everyday problems, so we fit that "wild bunch" into a systematic approach for variation-aware design, a designer's field guide and more. That is where this book can help! Circuit Design: Anticipate, Analyze, Exploit Variations starts with best-practise manual methods and links them tightly to up-to-date automation algorithms. We provide many tractable examples and explain key techniques you have to know. We then enable you to select and setup suitable methods for each design task - knowing their prerequisites, advantages and, as too often overlooked, their limitations as well. The good thing with computers is that you yourself can often verify amazing things with little effort, and you can use software not only to your direct advantage in solving a specific problem, but also for becoming a better skilled, more experienced engineer. Unfortunately, EDA design environments are not good at all to learn about advanced numerics. So with this book we also provide two apps for learning about statistic and optimization directly with circuit-related examples, and in real-time so without the long simulation times. This helps to develop a healthy statistical gut feeling for circuit design. The book is written for engineers, students in engineering and CAD / methodology experts. Readers should have some background in standard design techniques like entering a design in a schematic capture and simulating it, and also know about major technology aspects

Constraint-driven RF test stimulus generation and built-in test

With the explosive growth in wireless applications, the last decade witnessed an ever-increasing test challenge for radio frequency (RF) circuits. While the design community has pushed the envelope far into the future, by expanding CMOS process to be used with high-frequency wireless devices, test methodology has not advanced at the same pace. Consequently, testing such devices has become a major bottleneck in high-volume production, further driven by the growing need for tighter quality control. RF devices undergo testing during the prototype phase and during high-volume manufacturing (HVM). The benchtop test equipment used throughout prototyping is very precise yet specialized for a subset of functionalities. HVM calls for a different kind of test paradigm that emphasizes throughput and sufficiency, during which the projected performance parameters are measured one by one for each device by automated test equipment (ATE) and compared against defined limits called specifications. The set of tests required for each product differs greatly in terms of the equipment required and the time taken to test individual devices. Together with signal integrity, precision, and repeatability concerns, the initial cost of RF ATE is prohibitively high. As more functionality and protocols are integrated into a single RF device, the required number of specifications to be tested also increases, adding to the overall cost of testing, both in terms of the initial and recurring operating costs. In addition to the cost problem, RF testing proposes another challenge when these components are integrated into package-level system solutions. In systems-on-packages (SOP), the test problems resulting from signal integrity, input/output bandwidth (IO), and limited controllability and observability have initiated a paradigm shift in high-speed analog testing, favoring alternative approaches such as built-in tests (BIT) where the test functionality is brought into the package. This scheme can make use of a low-cost external tester connected through a low-bandwidth link in order to perform demanding response evaluations, as well as make use of the analog-to-digital converters and the digital signal processors available in the package to facilitate testing. Although research on analog built-in test has demonstrated hardware solutions for single specifications, the paradigm shift calls for a rather general approach in which a single methodology can be applied across different devices, and multiple specifications can be verified through a single test hardware unit, minimizing the area overhead. Specification-based alternate test methodology provides a suitable and flexible platform for handling the challenges addressed above. In this thesis, a framework that integrates ATE and system constraints into test stimulus generation and test response extraction is presented for the efficient production testing of high-performance RF devices using specification-based alternate tests. The main components of the presented framework are as follows: Constraint-driven RF alternate test stimulus generation: An automated test stimulus generation algorithm for RF devices that are evaluated by a specification-based alternate test solution is developed. The high-level models of the test signal path define constraints in the search space of the optimized test stimulus. These models are generated in enough detail such that they inherently define limitations of the low-cost ATE and the I/O restrictions of the device under test (DUT), yet they are simple enough that the non-linear optimization problem can be solved empirically in a reasonable amount of time. Feature extractors for BIT: A methodology for the built-in testing of RF devices integrated into SOPs is developed using additional hardware components. These hardware components correlate the high-bandwidth test response to low bandwidth signatures while extracting the test-critical features of the DUT. Supervised learning is used to map these extracted features, which otherwise are too complicated to decipher by plain mathematical analysis, into the specifications under test. Defect-based alternate testing of RF circuits: A methodology for the efficient testing of RF devices with low-cost defect-based alternate tests is developed. The signature of the DUT is probabilistically compared with a class of defect-free device signatures to explore possible corners under acceptable levels of process parameter variations. Such a defect filter applies discrimination rules generated by a supervised classifier and eliminates the need for a library of possible catastrophic defects.Ph.D.Committee Chair: Chatterjee, Abhijit; Committee Member: Durgin, Greg; Committee Member: Keezer, David; Committee Member: Milor, Linda; Committee Member: Sitaraman, Sures