Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Parametric Macromodels of Digital I/O Ports

This paper addresses the development of macromodels for input and output ports of a digital device. The proposed macromodels consist of parametric representations that can be obtained from port transient waveforms at the device ports via a well established procedure. The models are implementable as SPICE subcircuits and their accuracy and efficiency are verified by applying the approach to the characterization of transistor-level models of commercial devices

Behavioral Models of I/O Ports from Measured Transient Waveforms

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit ports from measured transient responses. The proposed approach is based on the estimation of parametric models from port voltage and current waveforms. The modeling process is described and applied to the modeling of output ports. Its feasibility is demonstrated by the identification of a real device from actual measurements, and by the comparison of the predicted device response with the measured one

Behavioral modeling of digital IC input and output ports

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to the characterization of actual device

Chaotic Oscillations in CMOS Integrated Circuits

Chaos is a purely mathematical term, describing a signal that is aperiodic and sensitive to initial conditions, but deterministic. Yet, engineers usually see it as an undesirable effect to be avoided in electronics. The first part of the dissertation deals with chaotic oscillation in complementary metal-oxide-semiconductor integrated circuits (CMOS ICs) as an effect behavior due to high power microwave or directed electromagnetic energy source. When the circuit is exposed to external electromagnetic sources, it has long been conjectured that spurious oscillation is generated in the circuits. In the first part of this work, we experimentally and numerically demonstrate that these spurious oscillations, or out-of-band oscillations are in fact chaotic oscillations. In the second part of the thesis, we exploit a CMOS chaotic oscillator in building a cryptographic source, a random number generator. We first demonstrate the presence of chaotic oscillation in standard CMOS circuits. At radio frequencies, ordinary digital circuits can show unexpected nonlinear responses. We evaluate a CMOS inverter coupled with electrostatic discharging (ESD) protection circuits, designed with 0.5 μm CMOS technology, for their chaotic oscillations. As the circuit is driven by a direct radio frequency injection, it exhibits a chaotic dynamics, when the input frequency is higher than the typical maximum operating frequency of the CMOS inverter. We observe an aperiodic signal, a broadband spectrum, and various bifurcations in the experimental results. We analytically discuss the nonlinear physical effects in the given circuit : ESD diode rectification, DC bias shift due to a non-quasi static regime operation of the ESD PN-junction diode, and a nonlinear resonant feedback current path. In order to predict these chaotic dynamics, we use a transistor-based model, and compare the model's performance with the experimental results. In order to verify the presence of chaotic oscillations mathematically, we build on an ordinary differential equation model with the circuit-related nonlinearities. We then calculate the largest Lyapunov exponents to verify the chaotic dynamics. The importance of this work lies in investigating chaotic dynamics of standard CMOS ICs that has long been conjectured. In doing so, we experimentally and numerically give evidences for the presence of chaotic oscillations. We then report on a random number generator design, in which randomness derives from a Boolean chaotic oscillator, designed and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic oscillator is given by the Boolean delay equation. According to numerical analysis of the Boolean delay equation, a single node network generates chaotic oscillations when two delay inputs are incommensurate numbers and the transition time is fast. To test this hypothesis physically, a discrete Boolean chaotic oscillator is implemented. Using a CMOS 0.5 μm process, we design and fabricate a CMOS Boolean chaotic oscillator which consists of a core chaotic oscillator and a source follower buffer. Chaotic dynamics are verified using time and frequency domain analysis, and the largest Lyapunov exponents are calculated. The measured bit sequences do make a suitable randomness source, as determined via National Institute of Standards and Technology (NIST) standard statistical tests version 2.1

Macromodeling strategy for digital devices and interconnects

International audienceThis paper proposes a macromodeling approach for the simulation of digital interconnected systems. Such an approach is based on a set of macromodels describing IC ports, IC packages and multiconductor interconnect structures in standard circuit simulators, like SPICE. We illustrate the features of the macromodels and we demonstrate the proposed approach on a realistic simulation problem

Integrated chaos generators

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.Comisión Interministerial de Ciencia y Tecnología 1FD97-1611(TIC)European Commission ESPRIT 3110

Oversampled analog-to-digital converter architectures based on pulse frequency modulation

Mención Internacional en el título de doctorThe purpose of this research work is providing new insights in the development of voltage-controlled oscillator based analog-to-digital converters (VCO-based ADCs). Time-encoding based ADCs have become of great interest to the designer community due to the possibility of implementing mostly digital circuits, which are well suited for current deep-submicron CMOS processes. Within this topic, VCO-based ADCs are one of the most promising candidates. VCO-based ADCs have typically been analyzed considering the output phase of the oscillator as a state variable, similar to the state variables considered in __ modulation loops. Although this assumption might take us to functional designs (as verified by literature), it does not take into account neither the oscillation parameters of the VCO nor the deterministic nature of quantization noise. To overcome this issue, we propose an interpretation of these type of systems based on the pulse frequency modulation (PFM) theory. This permits us to analytically calculate the quantization noise, in terms of the working parameters of the system. We also propose a linear model that applies to VCO-based systems. Thanks to it, we can determine the different error processes involved in the digitization of the input data, and the performance limitations which these processes direct to. A generic model for any order open-loop VCO-based ADCs is made based on the PFM theory. However, we will see that only the first-order case and a second order approximation can be implemented in practice. The PFM theory also allows us to propose novel approaches to both single-stage and multistage VCObased architectures. We describe open-loop architectures such as VCO-based architectures with digital precoding, PFM-based architectures that can be used as efficient ADCs or MASH architectures with optimal noise-transfer-function (NTF) zeros. We also make a first approach to the proposal and analysis of closed loop architectures. At the same time, we deal with one of the main limitations of VCOs (especially those built with ring oscillators), which is the non-linear voltage to- frequency relation. In this document, we describe two techniques mitigate this phenomenon. Firstly, we propose to use a pulse width modulator in front of the VCO. This way, there are only two possible oscillation states. Consequently, the oscillator works linearly. To validate the proposed technique, an experimental prototype was implemented in a 40-nm CMOS process. The chip showed noise problems that degraded the expected resolution, but allowed us to verify that the potential performance was close to the expected one. A potential signal-to-noise-distortion ratio (SNDR) equal to 56 dB was achieved in 20 MHz bandwidth, consuming 2.15 mW with an occupied area equal to 0.03 mm2. In comparison to other equivalent systems, the proposed architecture is simpler, while keeping similar power consumption and linearity properties. Secondly, we used a pulse frequency modulator to implement a second ADC. The proposed architecture is intrinsically linear and uses a digital delay line to increase the resolution of the converter. One experimental prototype was implemented in a 40-nm CMOS process using one of these architectures. Proper results were measured from this prototype. These results allowed us to verify that the PFM-based architecture could be used as an efficient ADC. The measured peak SNDR was equal to 53 dB in 20 MHz bandwidth, consuming 3.5 mW with an occupied area equal to 0.08 mm2. The architecture shows a great linearity, and in comparison to related work, it consumes less power and occupies similar area. In general, the theoretical analyses and the architectures proposed in the document are not restricted to any application. Nevertheless, in the case of the experimental chips, the specifications required for these converters were linked to communication applications (e.g. VDSL, VDSL2, or even G.fast), which means medium resolution (9-10 bits), high bandwidth (20 MHz), low power and low area.El propósito del trabajo presentado en este documento es aportar una nueva perspectiva para el diseño de convertidores analógico-digitales basados en osciladores controlados por tensión. Los convertidores analógico-digitales con codificación temporal han llamado la atención durante los últimos años de la comunidad de diseñadores debido a la posibilidad de implementarlos en su gran mayoría con circuitos digitales, los cuales son muy apropiados para los procesos de diseño manométricos. En este ámbito, los convertidores analógico-digitales basados en osciladores controlados por tensión son uno de los candidatos más prometedores. Los convertidores analógico-digitales basados en osciladores controlados por tensión han sido típicamente analizados considerando que la fase del oscilador es una variable de estado similar a las que se observan en los moduladores __. Aunque esta consideración puede llevarnos a diseños funcionales (como se puede apreciar en muchos artículos de la literatura), en ella no se tiene en cuenta ni los parámetros de oscilación ni la naturaleza determinística del ruido de cuantificación. Para solventar esta cuestión, en este documento se propone una interpretación alternativa de este tipo de sistemas haciendo uso de la teoría de la modulación por frecuencia de pulsos. Esto nos permite calcular de forma analítica las ecuaciones que modelan el ruido de cuantificación en función de los parámetros de oscilación. Se propone también un modelo lineal para el análisis de convertidores analógico-digitales basados en osciladores controlados por tensión. Este modelo permite determinar las diferentes fuentes de error que se producen durante el proceso de digitalización de los datos de entrada y las limitaciones que suponen. Un modelo genérico de convertidor de cualquier orden se propone con la ayuda de este modelo. Sin embargo, solo los casos de primer orden y una aproximación al caso de segundo orden se pueden implementar en la práctica. La teoría de la modulación por frecuencia de pulsos también permite nuevas perspectivas para la propuesta y el análisis tanto de arquitecturas de una sola etapa como de arquitecturas de varias etapas construidas con osciladores controlados por tensión. Se proponen y se describen arquitecturas en lazo abierto como son las basadas en osciladores controlador por tensión con moduladores digitales en la etapa de entrada, moduladores por frecuencia de pulsos que se utilizan como convertidores analógico-digitales eficientes o arquitecturas en cascada en las que se optimizan la distribución de los ceros en la función de transferencia del ruido. También se realiza una aproximación a la propuesta y el análisis de arquitecturas en lazo cerrado. Al mismo tiempo, se aborda una de las problemáticas más importantes de los osciladores controlados por tensión (especialmente en aquellos implementados mediante osciladores en anillo): la relación tensión-freculineal que presentan este tipo de circuitos. En el documento, se describen dos técnicas cuyo objetivo es mitigar esta limitación. La primera técnica de corrección se basa en el uso de un modulador por ancho de pulsos antes del oscilador controlado por tensión. De esta forma, solo existen dos estados de oscilación en el oscilador, se trabaja de forma lineal y no se genera distorsión en los datos de salida. La técnica se propone de forma teórica haciendo uso de la teoría desarrollada previamente. Para llevar a cabo la validación de la propuesta teórica se fabricó un prototipo experimental en un proceso CMOS de 40-nm. El chip mostró problemas de ruido que limitaban la resolución, sin embargo, nos permitió velicar que la resolución ideal que se podrá haber obtenido estaba muy cercana a la resolución esperada. Se obtuvo una potencial relación señal-(ruido-distorsión) igual a 56 dB en 20 MHz de ancho de banda, un consumo de 2.15 mW y un área igual a 0.03 mm2. En comparación con sistemas equivalentes, la arquitectura propuesta es más simple al mismo tiempo que se mantiene el consumo así como la linealidad. A continuación, se propone la implementación de un convertidor analógico digital mediante un modulador por frecuencia de pulsos. La arquitectura propuesta es intrínsecamente lineal y hace uso de una línea de retraso digital con el fin de mejorar la resolución del convertidor. Como parte del trabajo experimental, se fabricó otro chip en tecnología CMOS de 40 nm con dicha arquitectura, de la que se obtuvieron resultados notables. Estos resultados permitieron verificar que la arquitectura propuesta, en efecto, podrá emplearse como convertidor analógico-digital eficiente. La arquitectura consigue una relación real señal-(ruido-distorsión) igual a 53 dB en 20 MHz de ancho de banda, un consumo de 3.5 mW y un área igual a 0.08 mm2. Se obtiene una gran linealidad y, en comparación con arquitecturas equivalentes, el consumo es menor mientras que el área ocupada se mantiene similar. En general, las aportaciones propuestas en este documento se pueden aplicar a cualquier tipo de aplicación, independientemente de los requisitos de resolución, ancho de banda, consumo u área. Sin embargo, en el caso de los prototipos fabricados, las especificaciones se relacionan con el ámbito de las comunicaciones (VDSL, VDSL2, o incluso G.fast), en donde se requiere una resolución media (9-10 bits), alto ancho de banda (20 MHz), manteniendo bajo consumo y baja área ocupada.Programa Oficial de Doctorado en Ingeniería Eléctrica, Electrónica y AutomáticaPresidente: Michael Peter Kennedy.- Secretario: Antonio Jesús López Martín.- Vocal: Jörg Hauptman