This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to the characterization of actual device

Becker, D.

Canavero, Flavio

Chen, Z.

Katopis, G.

Maio, Ivano Adolfo

Stievano, Igor Simone

English

STIEVANO, IGOR SIMONE

CANAVERO, Flavio

MAIO, Ivano Adolfo

Chen Z.

Becker D.

Katopis G.

PORTO@iris (Publications Open Repository TOrino - Politecnico di Torino)

05 August 2020POLITECNICO DI TORINORepository ISTITUZIONALEBehavioral modeling of digital IC input and output ports / Stievano I.S.; Chen Z.; Becker D.; Canavero F.G.; Katopis G.;Maio I.A.. - STAMPA. - (2001), pp. 331-334. ((Intervento presentato al convegno Electrical Performance of ElectronicPackaging, 2001 tenutosi a Cambridge, MA (USA) nel Oct. 29-31, 2001.OriginalBehavioral modeling of digital IC input and output portsPublisher:PublishedDOI:10.1109/EPEP.2001.967675Terms of use:openAccessPublisher copyright(Article begins on next page)This article is made available under terms and conditions as specified in the  corresponding bibliographic description inthe repositoryAvailability:This version is available at: 11583/1413678 since:Piscataway, N.J. : IEEEBehavioral modeling of digital IC input and output ports I. S. Stievano', 2. Chen2, D. Becker2, F. G. Canaverol, G. Katopis2, I. A. Maiol Dip. Elettronica, Politecnico di Torino C. Duca degli Abruzzi 24, 10129 Torino, Italy IBM Enterprise System Group, Poughkeepsie, NY, USA, (e-mail zhaoqingous. ibm. corn) Ph. f39 011 5644184, Fax +39 011 5644099 (e-mail stievanoQpolito.it) Abstract:  This paper addresses the development of accurate and efficient .behavioral models of digital integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling process is described and applied to  the characterization of actual devices. 1 Introduction The development of behavioral models of digital Integrated Circuits (IC) ports is a key resource for the assessment of signal integrity (SI) effects on fast digital circuits. Such an assessment is mainly achieved by simulating the evolution of signals on interconnects and requires accurate and efficient models of IC ports. Behavioral models, that  are simplified models obtained from waveforms computed or measured at devices ports, match this requirement. In this paper we address the development of behavioral models via parametric representations, that offer interesting features. The estimation of parametric models can take into account all the physical effects relating port voltage and current, since their structure is selected by the estimation proces itself. Besides, the accuracy of such models is also weakly influenced by the external loads they are connected to. The modeling process is described and applied to the characterization of both input and output ports of commercial IBM devices. 2 Drivers models The modeling of a digital IC output port (driver hereafter) via a parametric model amounts to relate its port voltage and current by a suitable parametric equation. The equation must be nonstationary in order to take into account port logic state and state transitions. Various model representations are possible for such nonlinear time-dependent devices. After extensive search [I, 2, 6, 71, we recognized that the following discrete-time Piecewise (PW) representation provides an accurate model for drivers: i(k) = Wl(k)fl(k) + wz(k)f2@) (1) The above expression assumes that the port current i is obtained as a combination of two submodels f and f2 ,  reproducing the behavior of the driver in the High and Low output states, respectively. The combination coefficients are w1 and w2, that take into account driver state switchings. Submodels j l  and jz  are nonlinear dynamic parametric models, based on the theory of Radial Basis Functions (RBF) [3]. They consist of sums of gaussian basis functions depending on the past T samples of the port current i (T is called the dynamic order of the model), and the present and past samples of the port voltage v. Each basis function is properly centered in the parameters space and depends on the distance from centers. The estimation of model (1) is carried out by a simple procedure [2] and is done by matching the output of the model to  the output of actual drivers for suitable input signals. Port voltage and current waveforms involved in the estimation of parametric models are named identification signals. Submodels f l  and f2 are obtained via effective estimation algorithms [4, 51 whereas the weight coefficients w1 and w2 are estimated by linear inversion of (1) where v and i are replaced by sampled waveforms recorded on two different loads (identzfication loads) during the Up (Low-to-High) and the Down (High-to-Low) state switchings. This modeling process has been developed and validated by applying it to the characterization of several virtual and actual devices (1, 21. Besides, It has also been succesfully applied to  the characterization of commercial IBM drivers [SI. The last part of the process is the implementation of the estimated PW-RBF models (1) in a circuit simulation environment, like SPICE, by means of an equivalent circuit. This is achieved by converting 0-7803-7024-4/01/$10.00 0 2001 IEEE 33 1 equation (1) into a continuous time statespace model and then by synthesizing it via RC circuits with voltage controlled sources. In the following, we show two examples highlighting the accuracy and efficiency of PW-RBF models, estimated from detailed transistor-level models (reference models hereafter) of high speed IBM drivers. Example 1: The Modeled Driver (MD1) is an IBM CMOS driver (power supply: V,, = OV, Vdd = 1.65V) used in IBM mainframe products. The iden- tification loads for the estimation process are a 100 R and a 50 R resistor in series with a V ,  battery. The PW-RBF model estimated for MD1 has dynamic or- der r = 1 and a number of basis functions 9 for both submodels f1 and 1 2 .  sponses of MD1 and of its PW-RBF model when they apply a 4ns pulse (bit pattern ' tOIOt ' )  to three ideal transmission lines, with different characteristic impedance and time delay values, terminated by a 1 pF capacitor. The accuracy of the PW-RBF model in reproducing the reference behavior of MD1 for generic dynamic loads can be clearly appreciated. Exampl? 2: The Modeled Driver (MD2) is another IBM CMOS driver (Vss = ov, v,, = 1.5v)  used in IBM mainframe products and the identification loads are the same as those used in the Example 1. The PW-RBF model estimated for MD2 has dy- namic order T = 1, a number of nine basis functions for submodel fl and seven for submodel f ~ .  Figure 2 shows the validation setup devised for this second example. It is based on a three-conductor lossy on-MCM interconnect (2 lands + reference plane) driven by two MD2 devices and terminated by 1 p F  capacitors. The deviceon land #1 is active and sends a train pulse (bit pattern ~ ' 0 1 ~ 0 ~ ~ 1 0 ~ 0 ~ ~ 0 ~ 0 " ) ,  whereas the device on land #2 remains quiet in the Low logic state (bit pattern ' tO~OOOOOOOOOOO~O~') .  >2:;N>;; 2 o -1 0 1 2 3 4 5 6 7  As a validation test, Figure 1 compares the re- > E!?zz23 4 5 6  =o , rime ns Figure 1: Far-end voltage waveform q e ( t )  on three ideal transmission lines driven by MD1 (solid, reference Curve) and bY its PW-RBF model (dotted). Panel (a) refers to a line with ZC = 50 a, Td = 0.5 ns; (b) z c  = 1ooR, T d  = 0.5% (c) ZC = 1oOaj Td = 4oPS. 0 5 10 IS 20 25 30 rime ns Figure 2: Coupled-line structure for the realistic test case of Example 2 (length O.lm, 111 = Z22 = 0.441 pH/m, 112 = 121 = 14.4 nH/m, c11 = c22 = 144pF/m, c12 = c21 = -1.38pF/m, dc resistance 24.40/m, skin effect coefficient 11.7 R s-l/'/m, dielectric loss factor 2.5 Figure 3: Far-end voltage waveforms vzl(t) and vz2(t) on the active and quiet line of the structure of Fig. 2. Solid lines: reference responses; dotted lines: approx- imate responses obtained by PW-RBF models. Cr, = I p F )  332 Figure 3 shows the far-end voltage waveforms vzl(t) and u22(t)  on both the active and the quiet land of the setup. This comparison highlights that also the far-end crosstalk signal, which is a sensitive quantity, can be carefully predicted by using PW-RBF models. The estimation of PW-RBF models is rather fast and their numerical efficiency is fairly good. The CPU time needed to estimate the models of the above examples is some ten seconds on a Pentium-I1 PC @I 350 MHz. PW-RBF models turn out to be more than 20 times faster than transistor-level models and lead to timing errors that are always less than 5 + 20ps, being T, = 5 + l ops  the sampling time used in the estimation process. The above timing errors are obtained by computing the maximum delay between the crossing of a suitable voltage treshold of PW-RBF and reference transistor-level models responses. 3 Receivers models The development of behavioral models for input ports (receivers in the following) is rather straightforward because, in contrast with output ports, their operation is hardly influenced by the IC internal states. For input port voltages in the range of power supply, receivers exhibit a mainly linear capacitive behavior, whereas outside such range their behavior is dominated by the nonlinear protection circuits. This property and the physical structure of receivers suggest the following model representation i ( k )  = il(lc) +in&) where the current i flowing into the input pin is split into two contributions. The first part, 2 1 ,  is described by a linear AutoRegression with ex t ra  input (ARX) parametric model [8] defined by the linear combination of the present sample of the port voltage w, and the past r samples of w and i, being r the dynamic order of the model. Submodel il is obtained by standard estimation routines 19, 51 and suitable identification signals, obtained by driving the receiver with a voltage multilevel waveform spanning the range of the power supply. The second part, in[ ,  is a nonlinear model that accounts for the nonlinear behavior of receivers in the voltage range where the effects of protection cir- cuits are dominant. We found that a simple shunt connection of two identical circuits, each consisting of the series connection of an inductor and a non- linear resistor, leads to models performing with a sufficient accuracy. In this case, i , l  is defined by the following equation where g is the i - v static characteristic of the re- ceiver and L1 and Lz are the series inductors taking into account the dynamic behavior of receiver in the nonlinear regions where the protection circuits dom- inate. The values of the series inductors L1 and Lz are obtained by driving the receiver with a small signal voltage step for U > Vdd and w < V,,, respec- tively, and by solving a linear least squares prob- lem. This is done by minimizing the error between the reference response of the receiver and the model response. It is ought to remark that a simple circuit model I 2 4 6 8 10 0 2 4 6 8 IO time ns Figure 4: Results of validation tests for receivers (see text for details). Panel (a): model responses for a re- ceiver driven directly by an equivalent source. Panel (b)  and (c) :  model responses for a receiver driven through a transmission line. Solid lines: reference re- sponses; dotted lines: higher-order model responses; dashed line: i - w model response. - (referred to  as i - U model below) consisting of a shunt connection between a capacitor C, and a nonlinear resistor belongs to the class defined by (2). In fact, a capacitor and a nonlinear resistor are the simplest il and in[ submodels taking into account both the static and dynamic behavior of receivers. However, it can be verified that a capacitor gives only a rough approximation of the quasi-linear behavior of the port, having order r = 1. A better accuracy can be achieved by using submodels il of dynamic order r = 3 + 7 (higher-order models). Also, the choice of equation (3) for i ,l  arises from qualitative analyses of the behavior of modeled receivers. If necessary, the accuracy of the proposed model can be further improved by using nonlinear parametric models. 333 Finally, the estimated models (2) are turned into equivalent circuits and implemented as SPICElike subcircuits by following the same procedure described in Section 2. An example highlighting the accuracy of the above models, estimated from detailed transistor-level models of high speed IBM receivers, follows. Example 3: The Modeled Receiver (MR) is an IBM receiver (Vas = OV, Vdd = 1.5V) used in the same series of IBM products as those of the previous examples. For such a MR we estimated two different models (2): a simple i - v model ( r  = 1, C,, = 3pF) and an higher order model (T = 5, L1 N 8.39 nH, Lz N 7.27 nH). As a first validation test, we consider a setup consisting of the MR driven by the series connection of a 5 R resistor and an ideal voltage source producing a step (amplitude=lV, transition time=lOOps). For such a setup, Fig. 4, panel (a), shows the comparison between the MR i(t) reference response and estimated models responses. From the previous curves we can appreciate the improvement on the accuracy of higher-order models. As a second and more realistic validation test, we consider a lOcm long lossy transmission line loaded by the MR and driven by the series connection of a 300 resistor and an ideal voltage source producing a Ins  pulse (amplitude=Vdd, transition time=lOOps). Fig. 4, panel (b) and (c), shows the MR v(t) and i(t) reference responses and the responses generated by the higher-order model. Finally, we assessed the performances of the estimated models (2) (i.e., model generation time, timing errors, accuracy, efficiency), finding results similar to  those obtained in Section 2. 4 Conclusion This paper addresses the development of accurate and efficient behavioral models of both input and output ports of digital ICs. The proposed approach is based on the estimation of nonlinear parametric models from port current and voltage waveforms. The obtained models perform well on high speed actual devices. Their cost of generation is low and they can replace transistor-level models for the simulation of realistic SI problems without appreciable loss of accuracy. References [I] I. S. Stievano, I. A. Maio, “Behavioral models of digital IC ports from measured transient waveforms,” in gth IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP2000), Scottsdale, AZ, pp. 211-214, October 23-25, 2000. [2] F. G. Canavero, I. A. Maio, I. S. Stievano, “Black-Box Models of Digital IC ports for EMC simulations,” in 14 th IEEE International Zurich Symposium on Electromagnetic Compatibility, Zurich, CH, pp. 679-684, February 20-22, 2001. [3] J .  Sjoberg et al., “Nonlinear Black-Box Modeling in System Identification: a Unified Overview,” Auto- matica, Vol. 31, NO. 12, pp. 1691-1724, 1995. [4] S. Chen, C. F. N. Cowan and P. M. Grant, “Ortogonal Least Squares Learning Algorithm for Radial Basis Function Network,” IEEE Transactions on Neural Networks, Vol. 2, NO. 2, pp. 302-309, March 1991. [5] K. Judd and A. Mees, “On selecting models for nonlinear time series,” Physica D, Vol. 82, pp. 426-444, 1995. [6] I. S. Stievano, F. G. Canavero, 2. Chen, G. Katopis, I. A. Maio, “High Performance RBF Models of Digital Drivers,” in 5th IEEE Workshop on Signal Propagation on Interconnects, Venice, I, May 13-16, 2001. [7] F. G .  Canavero, I. A. Maio, I. S. Stievano, “Identification of Models for Digital Integrated Circuit Ports from Measured Transient Waveforms,” in IEEE Instrumentation and Measurement Technology Conference IMTC/2001, Budapest, Hungary, 21-23 May 2001. [8] L. Ljung, System identification: theory for the user. Prentice-Hall, 1987. 191 L. Ljung, System identification toolbox user’s guide (Ver. 5). The Mathworks, inc, November 2000. 334 

Behavioral modeling of digital IC input and output ports

PORTO Publications Open Repository TOrino

Behavioral modeling of digital IC input and output ports 
I. S. Stievano', 2. Chen2, D. Becker2, F. G. Canaverol, G. Katopis2, I. A. Maiol 
Dip. Elettronica, Politecnico di Torino C. Duca degli Abruzzi 24, 10129 Torino, Italy 
IBM Enterprise System Group, Poughkeepsie, NY, USA, (e-mail zhaoqingous. ibm. corn) 
Ph. f39 011 5644184, Fax +39 011 5644099 (e-mail stievanoQpolito.it) 
Abstract:  This paper addresses the development of accurate and efficient .behavioral models of digital 
integrated circuit input and output ports for signal integrity simulations and timing analyses. The modeling 
process is described and applied to  the characterization of actual devices. 
1 Introduction 
The development of behavioral models of digital Integrated Circuits (IC) ports is a key resource for the 
assessment of signal integrity (SI) effects on fast digital circuits. Such an assessment is mainly achieved by 
simulating the evolution of signals on interconnects and requires accurate and efficient models of IC ports. 
Behavioral models, that  are simplified models obtained from waveforms computed or measured at devices 
ports, match this requirement. 
In this paper we address the development of behavioral models via parametric representations, that offer 
interesting features. The estimation of parametric models can take into account all the physical effects 
relating port voltage and current, since their structure is selected by the estimation proces itself. Besides, 
the accuracy of such models is also weakly influenced by the external loads they are connected to. 
The modeling process is described and applied to the characterization of both input and output ports of 
commercial IBM devices. 
2 Drivers models 
The modeling of a digital IC output port (driver hereafter) via a parametric model amounts to relate its 
port voltage and current by a suitable parametric equation. The equation must be nonstationary in order 
to take into account port logic state and state transitions. Various model representations are possible for 
such nonlinear time-dependent devices. After extensive search [I, 2, 6, 71, we recognized that the following 
discrete-time Piecewise (PW) representation provides an accurate model for drivers: 
i(k) = Wl(k)fl(k) + wz(k)f2@) (1) 
The above expression assumes that the port current i is obtained as a combination of two submodels f and 
f2 ,  reproducing the behavior of the driver in the High and Low output states, respectively. The combination 
coefficients are w1 and w2, that take into account driver state switchings. Submodels j l  and jz  are nonlinear 
dynamic parametric models, based on the theory of Radial Basis Functions (RBF) [3]. They consist of sums 
of gaussian basis functions depending on the past T samples of the port current i (T is called the dynamic 
order of the model), and the present and past samples of the port voltage v. Each basis function is properly 
centered in the parameters space and depends on the distance from centers. 
The estimation of model (1) is carried out by a simple procedure [2] and is done by matching the output 
of the model to  the output of actual drivers for suitable input signals. Port voltage and current waveforms 
involved in the estimation of parametric models are named identification signals. Submodels f l  and f2 are 
obtained via effective estimation algorithms [4, 51 whereas the weight coefficients w1 and w2 are estimated 
by linear inversion of (1) where v and i are replaced by sampled waveforms recorded on two different loads 
(identzfication loads) during the Up (Low-to-High) and the Down (High-to-Low) state switchings. 
This modeling process has been developed and validated by applying it to the characterization of several 
virtual and actual devices (1, 21. Besides, It has also been succesfully applied to  the characterization of 
commercial IBM drivers [SI. 
The last part of the process is the implementation of the estimated PW-RBF models (1) in a circuit 
simulation environment, like SPICE, by means of an equivalent circuit. This is achieved by converting 
0-7803-7024-4/01/$10.00 0 2001 IEEE 33 1 
equation (1) into a continuous time statespace model and then by synthesizing it via RC circuits with 
voltage controlled sources. 
In the following, we show two examples highlighting the accuracy and efficiency of PW-RBF models, 
estimated from detailed transistor-level models (reference models hereafter) of high speed IBM drivers. 
Example 1: The Modeled Driver (MD1) is an IBM 
CMOS driver (power supply: V,, = OV, Vdd = 
1.65V) used in IBM mainframe products. The iden- 
tification loads for the estimation process are a 100 R 
and a 50 R resistor in series with a V ,  battery. The 
PW-RBF model estimated for MD1 has dynamic or- 
der r = 1 and a number of basis functions 9 for both 
submodels f1 and 1 2 .  
sponses of MD1 and of its PW-RBF model when 
they apply a 4ns pulse (bit pattern ' tOIOt ' )  to three 
ideal transmission lines, with different characteristic 
impedance and time delay values, terminated by a 
1 pF capacitor. The accuracy of the PW-RBF model 
in reproducing the reference behavior of MD1 for 
generic dynamic loads can be clearly appreciated. 
Exampl? 2: The Modeled Driver (MD2) is another 
IBM CMOS driver (Vss = ov, v,, = 1.5v)  used 
in IBM mainframe products and the identification 
loads are the same as those used in the Example 
1. The PW-RBF model estimated for MD2 has dy- 
namic order T = 1, a number of nine basis functions 
for submodel fl and seven for submodel f ~ .  
Figure 2 shows the validation setup devised for this second example. It is based on a three-conductor 
lossy on-MCM interconnect (2 lands + reference plane) driven by two MD2 devices and terminated by 1 p F  
capacitors. The deviceon land #1 is active and sends a train pulse (bit pattern ~ ' 0 1 ~ 0 ~ ~ 1 0 ~ 0 ~ ~ 0 ~ 0 " ) ,  whereas 
the device on land #2 remains quiet in the Low logic state (bit pattern ' tO~OOOOOOOOOOO~O~') .  
>2:;N
>;; 
2 o 
-1 
0 1 2 3 4 5 6 7  
As a validation test, Figure 1 compares the re- > E!?zz23 
4 5 6  
=o 
, 
rime ns 
Figure 1: Far-end voltage waveform q e ( t )  on three 
ideal transmission lines driven by MD1 (solid, reference 
Curve) and bY its PW-RBF model (dotted). Panel 
(a) refers to a line with ZC = 50 a, Td = 0.5 ns; (b) 
z c  = 1ooR, T d  = 0.5% (c) ZC = 1oOaj Td = 4oPS. 
0 5 10 IS 20 25 30 
rime ns 
Figure 2: Coupled-line structure for the realistic 
test case of Example 2 (length O.lm, 111 = Z22 = 
0.441 pH/m, 112 = 121 = 14.4 nH/m, c11 = c22 = 
144pF/m, c12 = c21 = -1.38pF/m, dc resistance 
24.40/m, skin effect coefficient 11.7 R s-l/'/m, 
dielectric loss factor 2.5 
Figure 3: Far-end voltage waveforms vzl(t) and vz2(t) 
on the active and quiet line of the structure of Fig. 2. 
Solid lines: reference responses; dotted lines: approx- 
imate responses obtained by PW-RBF models. 
Cr, = I p F )  
332 
Figure 3 shows the far-end voltage waveforms vzl(t) and u22(t)  on both the active and the quiet land of 
the setup. This comparison highlights that also the far-end crosstalk signal, which is a sensitive quantity, can 
be carefully predicted by using PW-RBF models. 
The estimation of PW-RBF models is rather fast and their numerical efficiency is fairly good. The CPU 
time needed to estimate the models of the above examples is some ten seconds on a Pentium-I1 PC @I 350 MHz. 
PW-RBF models turn out to be more than 20 times faster than transistor-level models and lead to timing 
errors that are always less than 5 + 20ps, being T, = 5 + l ops  the sampling time used in the estimation 
process. The above timing errors are obtained by computing the maximum delay between the crossing of a 
suitable voltage treshold of PW-RBF and reference transistor-level models responses. 
3 Receivers models 
The development of behavioral models for input ports (receivers in the following) is rather straightforward 
because, in contrast with output ports, their operation is hardly influenced by the IC internal states. 
For input port voltages in the range of power supply, receivers exhibit a mainly linear capacitive behavior, 
whereas outside such range their behavior is dominated by the nonlinear protection circuits. This property 
and the physical structure of receivers suggest the following model representation 
i ( k )  = il(lc) +in&) 
where the current i flowing into the input pin is split into two contributions. The first part, 2 1 ,  is described 
by a linear AutoRegression with ex t ra  input (ARX) parametric model [8] defined by the linear combination 
of the present sample of the port voltage w, and the past r samples of w and i, being r the dynamic order of 
the model. Submodel il is obtained by standard estimation routines 19, 51 and suitable identification signals, 
obtained by driving the receiver with a voltage multilevel waveform spanning the range of the power supply. 
The second part, in[ ,  is a nonlinear model that 
accounts for the nonlinear behavior of receivers in 
the voltage range where the effects of protection cir- 
cuits are dominant. We found that a simple shunt 
connection of two identical circuits, each consisting 
of the series connection of an inductor and a non- 
linear resistor, leads to models performing with a 
sufficient accuracy. In this case, i , l  is defined by 
the following equation 
where g is the i - v static characteristic of the re- 
ceiver and L1 and Lz are the series inductors taking 
into account the dynamic behavior of receiver in the 
nonlinear regions where the protection circuits dom- 
inate. The values of the series inductors L1 and Lz 
are obtained by driving the receiver with a small 
signal voltage step for U > Vdd and w < V,,, respec- 
tively, and by solving a linear least squares prob- 
lem. This is done by minimizing the error between 
the reference response of the receiver and the model 
response. 
It is ought to remark that a simple circuit model 
I 
2 4 6 8 10 
0 2 4 6 8 IO 
time ns 
Figure 4: Results of validation tests for receivers (see 
text for details). Panel (a): model responses for a re- 
ceiver driven directly by an equivalent source. Panel 
(b)  and (c) :  model responses for a receiver driven 
through a transmission line. Solid lines: reference re- 
sponses; dotted lines: higher-order model responses; 
dashed line: i - w model response. 
- 
(referred to  as i - U model below) consisting of a shunt connection between a capacitor C, and a nonlinear 
resistor belongs to the class defined by (2). In fact, a capacitor and a nonlinear resistor are the simplest 
il and in[ submodels taking into account both the static and dynamic behavior of receivers. However, it 
can be verified that a capacitor gives only a rough approximation of the quasi-linear behavior of the port, 
having order r = 1. A better accuracy can be achieved by using submodels il of dynamic order r = 3 + 7 
(higher-order models). Also, the choice of equation (3) for i ,l  arises from qualitative analyses of the behavior 
of modeled receivers. If necessary, the accuracy of the proposed model can be further improved by using 
nonlinear parametric models. 
333 
Finally, the estimated models (2) are turned into equivalent circuits and implemented as SPICElike 
subcircuits by following the same procedure described in Section 2. An example highlighting the accuracy of 
the above models, estimated from detailed transistor-level models of high speed IBM receivers, follows. 
Example 3: The Modeled Receiver (MR) is an IBM receiver (Vas = OV, Vdd = 1.5V) used in the same 
series of IBM products as those of the previous examples. For such a MR we estimated two different models 
(2): a simple i - v model ( r  = 1, C,, = 3pF) and an higher order model (T = 5, L1 N 8.39 nH, Lz N 7.27 nH). 
As a first validation test, we consider a setup consisting of the MR driven by the series connection of a 5 R 
resistor and an ideal voltage source producing a step (amplitude=lV, transition time=lOOps). For such a 
setup, Fig. 4, panel (a), shows the comparison between the MR i(t) reference response and estimated models 
responses. From the previous curves we can appreciate the improvement on the accuracy of higher-order 
models. 
As a second and more realistic validation test, we consider a lOcm long lossy transmission line loaded 
by the MR and driven by the series connection of a 300 resistor and an ideal voltage source producing a 
Ins  pulse (amplitude=Vdd, transition time=lOOps). Fig. 4, panel (b) and (c), shows the MR v(t) and i(t) 
reference responses and the responses generated by the higher-order model. 
Finally, we assessed the performances of the estimated models (2) (i.e., model generation time, timing 
errors, accuracy, efficiency), finding results similar to  those obtained in Section 2. 
4 Conclusion 
This paper addresses the development of accurate and efficient behavioral models of both input and output 
ports of digital ICs. The proposed approach is based on the estimation of nonlinear parametric models from 
port current and voltage waveforms. The obtained models perform well on high speed actual devices. Their 
cost of generation is low and they can replace transistor-level models for the simulation of realistic SI problems 
without appreciable loss of accuracy. 
References 
[I] I. S. Stievano, I. A. Maio, “Behavioral models of digital IC ports from measured transient waveforms,” in 
gth IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP2000), Scottsdale, 
AZ, pp. 211-214, October 23-25, 2000. 
[2] F. G. Canavero, I. A. Maio, I. S. Stievano, “Black-Box Models of Digital IC ports for EMC simulations,” in 
14 th IEEE International Zurich Symposium on Electromagnetic Compatibility, Zurich, CH, pp. 679-684, 
February 20-22, 2001. 
[3] J .  Sjoberg et al., “Nonlinear Black-Box Modeling in System Identification: a Unified Overview,” Auto- 
matica, Vol. 31, NO. 12, pp. 1691-1724, 1995. 
[4] S. Chen, C. F. N. Cowan and P. M. Grant, “Ortogonal Least Squares Learning Algorithm for Radial Basis 
Function Network,” IEEE Transactions on Neural Networks, Vol. 2, NO. 2, pp. 302-309, March 1991. 
[5] K. Judd and A. Mees, “On selecting models for nonlinear time series,” Physica D, Vol. 82, pp. 426-444, 
1995. 
[6] I. S. Stievano, F. G. Canavero, 2. Chen, G. Katopis, I. A. Maio, “High Performance RBF Models of 
Digital Drivers,” in 5th IEEE Workshop on Signal Propagation on Interconnects, Venice, I, May 13-16, 
2001. 
[7] F. G .  Canavero, I. A. Maio, I. S. Stievano, “Identification of Models for Digital Integrated Circuit Ports 
from Measured Transient Waveforms,” in IEEE Instrumentation and Measurement Technology Conference 
IMTC/2001, Budapest, Hungary, 21-23 May 2001. 
[8] L. Ljung, System identification: theory for the user. Prentice-Hall, 1987. 
191 L. Ljung, System identification toolbox user’s guide (Ver. 5). The Mathworks, inc, November 2000. 
334 


Behavioral models of digital IC ports from measured transient waveforms,”

High Performance

Identification of Models for Digital Integrated Circuit Ports from Measured Transient Waveforms,”

Nonlinear Black-Box Modeling in System Identification:

On selecting models for nonlinear time series,”

Ortogonal Least Squares Learning Algorithm for Radial Basis Function Network,”

System identification: theory for the user. Prentice-Hall,

https://iris.polito.it/retrieve/handle/11583/1413678/46445/cnf-2001-epep-rbf-IEEE.pdf

Behavioral modeling of digital IC input and output ports

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PORTO Publications Open Repository TOrino