Design, Fabrication and Characterization of GaN HEMTs for Power Switching Applications

The unique properties of the III-nitride heterostructure, consisting of gallium nitride (GaN), aluminium nitride (AlN) and their ternary compounds (e.g. AlGaN, InAlN), allow for the fabrication of high electron mobility transistors (HEMTs). These devices exhibit high breakdown fields, high electron mobilities and small parasitic capacitances, making them suitable for wireless communication and power electronic applications. In this work, GaN-based power switching HEMTs and low voltage, short-channel HEMTs were designed, fabricated, and characterized.In the first part of the thesis, AlGaN/GaN-on-SiC high voltage metal-insulator-semiconductor (MIS)HEMTs fabricated on a novel ‘buffer-free’ heterostructure are presented. This heterostructure effectively suppresses buffer-related trapping effects while maintaining high electron confinement and low leakage currents, making it a viable material for high voltage, power electronic HEMTs. This part of the thesis covers device processing techniques to minimize leakage currents and maximize breakdown voltages in these ‘buffer-free’ MISHEMTs. Additionally, a recess-etched, Ta-based, ohmic contact process was utilized to form low-resistive ohmic contacts with contact resistances of 0.44-0.47 Ω∙mm. High voltage operation can be achieved by employing a temperature-stable nitrogen implantation isolation process, which results in three-terminal breakdown fields of 98-123 V/μm. By contrast, mesa isolation techniques exhibit breakdown fields below 85 V/μm and higher off-state leakage currents. Stoichiometric low-pressure chemical vapor deposition (LPCVD) SiNx passivation layers suppress gate currents through the AlGaN barrier below 10 nA/mm over 1000 V, which is more than two orders of magnitude lower compared to Si-rich SiNx passivation layers. A 10% dynamic on-resistance increase at 240 V was measured in HEMTs with stoichiometric SiNx passivation, which is likely caused by slow traps with time constants over 100 ms. SiNx gate dielectrics display better electrical isolation at high voltages compared to HfO2 and Ta2O5. However, the two gate oxides exhibit threshold voltages (Vth) above -2 V, making them a promising alternative for the fabrication of recess-etched normally-off MISHEMTs.Reducing the gate length (Lg) to minimize losses and increase the operating frequency in GaN HEMTs also entails more severe short-channel effects (SCEs), limiting gain, output power and the maximum off-state voltage. In the second part of the thesis, SCEs were studied in short-channel GaN HEMTs using a drain-current injection technique (DCIT). The proposed method allows Vth to be obtained for a wide range of drain-source voltages (Vds) in one measurement, which then can be used to calculate the drain-induced barrier lowering (DIBL) as a rate-of-change of Vth with respect to Vds. The method was validated using HEMTs with a Fe-doped GaN buffer layer and a C-doped AlGaN back-barrier with thin channel layers. Supporting technology computer-aided design (TCAD) simulations indicate that the large increase in DIBL is caused by buffer leakage. This method could be utilized to optimize buffer design and gate lengths to minimize on-state losses and buffer leakage currents in power switching HEMTs

Optimization of Ohmic Contacts and Surface Passivation for ‘Buffer-Free’ GaN HEMT Technologies

Gallium nitride high electron mobility transistors (GaN HEMTs) draw attention from high frequency and high power industries due to unique properties including high electron mobility and saturation velocity combined with high breakdown voltage. This makes GaN HEMTs suitable for power devices with high switching speed and high frequency applications with high power density requirements. However, the device performance is still partly limited by problems associated with the formation of low resistivity ohmic contact, trapping effects, and the confinement of the two-dimensional electron gas (2DEG).\ua0\ua0\ua0 In this work, reproducible deeply recessed Ta-based ohmic contacts with a low contact resistance of 0.2 - 0.3 Ωmm, a low annealing temperature of 550 - 600 \ub0C, and a large process window were optimized. Low annealing temperature reduces the risk of 2DEG degradation and promotes better morphology of the ohmic contacts. Deeply recessed ohmic contacts beyond the barrier layers make the process less sensitive to the etching depth since the ohmic contacts are formed on the sidewall of the recess. The concept of deeply recessed low resistivity ohmic contacts is also successfully demonstrated on different epi-structures with different barrier designs.\ua0\ua0\ua0 Passivation with silicon nitride (SiN) is an effective method to suppress electron trapping effects. Low Pressure Chemical Vapor Deposition (LPCVD) of SiN has shown to result in high quality dielectrics with excellent passivation effect. However, the surface traps are not fully removed after passivation due to dangling-bonds and native oxide layer at the interface of passivation and epi-structure. Therefore, a plasma-free in-situ NH3 pretreatment method before the deposition of the SiN passivation was studied. The samples with the pretreatment present a 38% lower surface-related current collapse and a 50% lower dynamic on-resistance than the samples without the pretreatment. The improved dynamic performance and lower dispersion directly yield a 30% higher output power of (3.4 vs. 2.6 W/mm) and a better power added efficiency (44% vs. 39%) at 3 GHz. Furthermore, it was found that a longer pretreatment duration improves the uniformity of device performance.\ua0\ua0\ua0 Traditionally, decreasing leakage currents in the buffer and improving electron confinement to the 2DEG are achieved by intentional acceptor-like dopants (iron and carbon) in the GaN buffer and back-barrier layer made by a ternary III-nitride material. However, electron trapping effects and thermal resistivity increase due to the dopants and the ternary material, respectively. In this thesis, a novel approach, where a unique epitaxial scheme permits a thickness reduction of the unintentional-doped (UID) GaN layer down to 250 nm, as compared to a normal thickness of 2 μm. In this way, the AlN nucleation layer effectively act as a back-barrier. The approached, named QuanFINE is investigated and benchmarked to a conventional epi-structure with a thick Fe-doped-GaN buffer. A 2DEG mobility of 2000 cm^2/V-s and the 2DEG concentration of 1.1∙10^13 cm^-2 on QuanFINE indicate that the 2DEG properties are not sacrificed with a thin UID-GaN layer. Thanks to the thin UID-GaN layer of QuanFINE, trapping effects are reduced. Comparable output power of 4.1 W/mm and a PAE of 40% at 3 GHz of both QuanFINE and conventional Fe-doped thick GaN buffer sample are measured

Control of threshold voltage in E-mode and D-mode GaN-on-Si metal-insulator-semiconductor heterostructure field effect transistors by in-situ fluorine doping of atomic layer deposition Al2O3 gate dielectrics

We report the modification and control of threshold voltage in enhancement and depletion mode AlGaN/GaN metal-insulator-semiconductor heterostructure field effect transistors through the use of in-situ fluorine doping of atomic layer deposition Al2O3. Uniform distribution of F ions throughout the oxide thickness are achievable, with a doping level of up to 5.5 × 1019 cm−3 as quantified by secondary ion mass spectrometry. This fluorine doping level reduces capacitive hysteretic effects when exploited in GaN metal-oxide-semiconductor capacitors. The fluorine doping and forming gas anneal also induces an average positive threshold voltage shift of between 0.75 and 1.36 V in both enhancement mode and depletion mode GaN-based transistors compared with the undoped gate oxide via a reduction of positive fixed charge in the gate oxide from +4.67 × 1012 cm−2 to −6.60 × 1012 cm−2. The application of this process in GaN based power transistors advances the realisation of normally off, high power, high speed devices

集積化AlGaN/GaNイオン感応性電界効果トランジスタに関する研究

AlGaN/GaN heterostructure ion-sensitive field-effect transistors (ISFETs) can provide high sensitivity and fast response due to the high electron mobility and high electron density providing by the two-dimensional electron gas (2DEG) generated at the AlGaN/GaN heterostructure interface. My research mainly focuses on the investigation of the integrated AlGaN/GaN ISFETs for pH sensing. To achieve high performance on AlGaN/GaN ISFET pH sensor, we fabricated sensors with different Al composition (25%, and 35%). We compared the characteristics of the sensors with 25% and 35% Al composition. The pH sensor with Al composition (35%) in the barrier layer with a 16 nm transition layer of 25% Al composition shows better surface sensitivity (SV) of 56.01 mV/pH, which is higher than that of the sensor with 25% Al composition (53.94 mV /pH), but worse current sensitivity SA (-0.095 mA/pH Vs -0.102 mA/pH). In addition, threshold voltage increases from approximately -1.6 V to approximately -0.8 V when measured in alkaline solution for 5 times, along with a decreasing output current. High-resolution SEM photos show that there are high density hexagonal pits with the size of approximately 100 nm on the device surface, presenting the etching effect along the dislocations during alkaline sensing. The X-ray photoelectron spectroscopy (XPS) demonstrates that the intensity of the Ga3d and Al2p spectra decreases after pH sensing measurement, implying the variation of chemical component occurs in the upper AlGaN thin layer. Many voids with a size of approximately 100 nm were observed from the transmission electron microscope (TEM) pictures, which are comparable with that of the scanning electron microscope (SEM). Combining with the energy dispersive X-ray spectroscopy (EDX), the degradation in electrical performance can be attributed to the transformation of AlGaN into oxide as well as the followed alkaline solution dissolve. To avoid the reaction of surface Al with solution, a 3 nm GaN cap layer was added. To reduce the barrier layer thickness, a recessed gate with a length of 2 μm and a depth of about 14 nm was formed. The current sensitivity of the AlGaN/GaN ISFET pH sensors has been improved by 61%, from 52.25 to 84.39 μA/pH, by the recessed-gate structure and ammoniate water treatment. A pH meter system based on the GaN pH sensor was constructed and evaluated. GaN-based ISFET can measure the pH value of the solutions with similar circuit, whether in the linear region or the saturation region. The measurement is stable and repeatable. The small current in the linear region can make the measurement stable and fast, but the resolution is a bit low. High resolution can be obtained in the saturation region, but the measurement is unstable due to excessive current. The Schottky barrier diode (SBD) based on GaN can be used for temperature sensing, and the temperature sensitivity can be improved by different structure design. A recessed anode AlGaN/GaN SBD is suitable to integrate with GaN-based power device for temperature sensor application. The temperature dependent forward voltage at a fixed current shows good linearity, resulting in a sensitivity of approximately 1.0 mV/K. The p-NiO guard ring can suppress the electric field at the anode/GaN interface and field crowding at the anode edge effectively, which enhances the breakdown voltage to approximately -250 V. Using the same material, we can design an integrated device sensor based on GaN to measure temperature and pH simultaneously, which will solve the measurement deviation of pH sensor at different temperatures

Device Design Parameterization of III-V Multi-Gate FETs

The use of group III-V semiconductor materials promise superior performance compared to silicon and can be considered a fundamental paradigm shift away from mature silicon technology. Group III-V semiconductors allow for high power operation, drastically high clock speeds, large breakdown fields, and higher Johnson’s Figure of Merit (JFoM). Due to higher electron drift velocity (vd) of the material set, higher on-state current (Ion) is expected than the one in silicon with reduced supply voltage operation. Additionally, strong spontaneous and piezoelectric polarization properties in the III-Nitrides support tighter carrier confinement with high carrier density in a quantum well channel at the heterointerface. By engineering the III-nitride properties, designing a 3D architecture device includes important physical parameters that must be taken into account to analyze device performance. GaN-based devices are desirable for high RF and high power applications for reducing parasitics and improving efficiency. For this reason, III-nitride semiconductor materials provide the possibility of future integration of GaN fin-based 3D devices. This dissertation describes the experimental realization and electrical analysis of III-V FinFET devices with an AlGaN/GaN heterostructure, called “Multi-Gate Heterostructure Fin Field Effect Transistor (MUG-HFinFET).” Process development begins with the experimental demonstration of a Si-compatible baseline AlGaN/GaN FinFET technology, and an exploration of the impact of physical device design parameters such as fin widths, heights, angles and gate lengths. The ohmic contact formation on AlGaN/GaN heterostructure is realized using different metal stacks while taking into account additional annealing effects and produces comparably low contact resistance to other literature reports. Different fabrication processes to distinguish the impact of the device architectures are demonstrated while simultaneously applying for the integration of high-k dielectric metal-gate stack including surface clean and passivation techniques developed for high quality interfaces and low-leakage performance. After MUG-HFinFET technology is implemented and characterized, the impacts of the device design parameters are benchmarked and shows the guidance to device design at the initial stage forward proper device application. The work concludes by assessing the novel characteristics of AlGaN/GaN heterostructure FinFET devices for 3D device design with distinguished performance. According to the distinguished performance across the device geometries and crystal directions, the benchmarks made in this dissertation will guide future device application development toward an AlGaN/GaN FinFET device design to ensure that a proper device design is achieved

AlGaN/GaN 전력소자의 특성 향상을 위한 식각과 절연막에 관한 연구

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2020. 8. 서광석.최근 에너지 위기와 환경규제 강화, 친환경 녹색성장 등의 이슈가 대두되어 에너지 절감과 환경 보호 분야에 IT 기술을 접목, 활용하는 그린 IT 패러다임이 부각되고 있다. 현재 고유가 환경규제 강화에 대응하기 위해 하이브리드 자동차, 전기자동차 등 친환경 미래형 자동차 개발이 요구되고 있으며, 자동차에서 전장부품이 차지하는 원가비중은 약 40%까지 달할 것으로 전망되고 이 중 반도체가 차지하는 비용은 약 30% 정도로 추정된다. 이러한 자동차 전장부품에서 전력소자가 핵심부품으로 자리 잡을 전망이다. 지금까지는 실리콘 기반의 전력소자 기술이 전력반도체 시장의 대부분을 주도하고 있지만 전력기기 로드맵에 의하면 전력밀도가 해를 거듭하면서 지속적으로 증가하기 때문에 내열, 내압, 전력손실, 전력밀도 등에서 나타나는 많은 한계를 가지고 있는 현재의 실리콘 기반 전력시스템은 효율이 눈에 띄게 감소할 것이 자명하므로 전력시스템의 전력전송효율과 신뢰성의 중요성이 크게 대두되고 있다. 이 같은 사회적 요구로 볼 때 현재의 실리콘 전력소자의 기술적 한계를 뛰어넘는 고효율의 차세대 전력반도체 소자의 개발이 시급히 요구되며 SiC와 GaN와 같은 광대역 반도체가 차세대 전력반도체 소재로 유력해지고 있다. 또한 전력시스템에서는 시스템의 안전성과 회로의 간략화를 위하여 normally-off (증강형) 전력소자가 요구되기 때문에 normally-off (증강형) GaN 전력소자에 대한 개발이 필수적이다. 본 그룹에서는 gate-recess 공정을 이용하여 normally-off 동작을 실현하는 연구를 진행하였고, gate-recess 시 발생하는 식각 데미지를 줄이고 우수한 성능의 게이트 절연막을 개발하여 GaN 전력 반도체 소자의 전기적 특성 및 신뢰성을 개선하는 연구를 진행하였다. 식각 연구에서는 최종적으로 셀프 DC 바이어스가 낮은 O2, BCl3 플라즈마를 이용한 atomic layer etching을 개발하였고, 이를 통해 거칠기가 작고 표면 N vacancy가 적은 고품질의 (Al)GaN 표면을 얻을 수 있었다. 박막 연구에서는 Oxide 박막 증착 시, (Al)GaN 표면에 생성되어 계면 특성을 악화시키는 Ga2O3 생성을 막기위해 ALD AlN layer를 개발 및 적용하여 박막/(Al)GaN 계면 특성을 향상시켰다. 이로 인해 소자의 동작전류 증가 및 Dit 감소 결과를 얻을 수 있었고 스트레스에 따른 문턱전압 이동 특성의 감소로 소자의 신뢰성 또한 개선시킬 수 있었다. 이는 타 기관의 결과와 비교해도 뒤떨어지지 않는 우수한 특성을 보여주었다. 결론적으로 본 연구의 작은 플라즈마 데미지를 갖는 식각공정과 고품질 절연막 개발을 통해 우수한 특성의 GaN 전력소자를 구현할 수 있었고 향후 차세대 전력소자에 적용을 위한 가능성을 확보하였다.The Si technology for power devices have already approached its theoretical limitations due to its physical and material properties, despite the considerable efforts such as super junction MOSFET, trench gate, and insulated gate bipolar transistors. To overcome these limitations, many kinds of compound materials such as GaN, GaAs, SiC, Diamond and InP which have larger breakdown voltage and high electron velocity than Si also have been studied as future power devices. GaN has been considered as a breakthrough in power applications due to its high critical electric field, high saturation velocity and high electron mobility compared to Si, GaAs, and SiC. Especially, AlGaN/GaN heterostructure field-effect transistors (HFETs) have been considered as promising candidates for high power and high voltage applications. However, these AlGaN/GaN heterostructure field-effect transistors with the 2DEG are naturally normally-on, which makes the devices difficult to deplete the channel at zero gate bias. Among the various methods for normally-off operation of GaN devices, gate-recess method is a promising method because it can be easier to implement than other approaches and ensure normally-off operation. However, charge trapping at the interface between gate dielectric and (Al)GaN and in the gate dielectric is a big issue for recessed gate MIS-HEMTs. This problem leads to degradation of channel mobility, on-resistance and on-current of the devices. Especially, Vth hysteresis after a positive gate voltage sweep and Vth shift under a gate bias stress are important reliability challenges in gate recessed MIS-HEMTs. The scope of this work is mainly oriented to achieve high quality interface at dielectric/(Al)GaN MIS by studying low damage etching methods and the ALD process of various dielectric layers. In the etching study, various etching methods for normally-off operation have been studied. Also, etching damage was evaluated by various methods such as atomic force microscopy (AFM), photoluminescence (PL) measurements, X-ray photoelectron spectroscopy (XPS) measurements and electrical properties of the recessed schottky devices. Among the etching methods, the ALE shows the smoothest etched surface, the highest PL intensity and N/(Al+Ga) ratio of the etched AlGaN surface and the lowest leakage current of the gate recessed schottky devices. It is suggested that the ALE is a promising etching technique for normally-off gate recessed AlGaN/GaN MIS-FETs. In the study of dielectrics, excellent electrical characteristics and small threshold volt¬age drift under positive gate bias stress are achieved by employing the SiON interfacial layer. However, considerable threshold voltage drift is observed under the higher positive gate bias stress even at the devices using the SiON interfacial layer. For further improvement of interface and reliability of devices, we develop and optimize an ALD AlN as an interfacial layer to avoid the formation of poor-quality oxide at the dielectric/(Al)GaN interface. We also develop an ALD AlHfON as a bulk layer, which have a high dielectric constant and low leakage current and high breakdown field characteristics. Devices with AlN/AlON/AlHfON layer show smaller I-V hysteresis of ~10 mV than that of devices with AlON/AlHfON layer. The extracted static Ron values of devices with AlN/AlON/AlHfON and AlON/AlHfON are 1.35 and 1.69 mΩ·cm2, respectively. Besides, the effective mobility, Dit and threshold voltage instability characteristics are all improved by employing the ALD AlN. In conclusion, for high performance and improvement of reliability of normally-off AlGaN/GaN MIS-FETs, this thesis presents an etching technique for low damage etching and high-quality gate dielectric layer and suggests that the ALE and ALD AlN/AlON/AlHfON gate dielectric are very promising for the future normally-off AlGaN/GaN MIS-FETsChapter 1. Introduction 1 1.1. Backgrounds 1 1.2. Normally-off Operation in AlGaN/GaN HFETs 3 1.3. Issues and Feasible Strategies in AlGaN/GaN MIS-HFETs 11 1.4. Research Aims 15 1.5. References 17 Chapter 2. Development and Evaluation of Low Damage Etching processes 22 2.1. Introduction 22 2.2. Various Evaluation Methods of Etching Damage 24 2.3. Low-Damage Dry Etching Methods 29 2.3.1. Inductively Coupled Plasma-Reactive Ion Etching Using BCl3/Cl2 Gas Mixture 29 2.3.2. Digital Etching Using Plasma Asher and HCl 34 2.3.3. Atomic Layer Etching Using Inductively Coupled Plasma–Reactive Ion Etching System (ICP-RIE) 50 2.4. Conclusion 75 2.5. References 76 Chapter 3. SiON/HfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 80 3.1. Introduction 80 3.2. ALD Processes for SiON and HfON 83 3.3. Electrical Characteristics of ALD SiON, HfON and SiON/HfON Dual Layer on n-GaN 87 3.4. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with SiON/HfON Dual Layer 95 3.5. Conclusion 113 3.6. References 114 Chapter 4. High Quality AlN/AlON/AlHfON Gate Dielectric Layer by ALD for AlGaN/GaN MIS-FETs 120 4.1. Introduction 120 4.2. Development of ALD AlN/AlON/AlHfON Gate Stack 122 4.2.1. Process Optimization for ALD AlN 122 4.2.2. ALD AlN as an Interfacial Layer 144 4.2.3. Thickness Optimization of AlN/AlON/ AlHfON Layer 149 4.2.4. ALD AlHfON Optimization 159 4.2.5. Material Characteristics of AlN/AlON/AlHfON Layer 167 4.3. Device Characteristics of Normally-off AlGaN/GaN MIS-FETs with AlN/AlON/AlHfON Layer 171 4.4. Conclusion 182 4.5. References 183 Chapter 5. Concluding Remarks 188 Appendix. 190 A. N2 Plasma Treatment Before Dielectric Deposition 190 B. Tri-gate Normally-on/off AlGaN/GaN MIS-FETs 200 C. AlGaN/GaN Diode with MIS-gated Hybrid Anode and Edge termination 214 Abstract in Korean 219 Research Achievements 221Docto

Fabrication and Characterization of AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors for High Power Applications

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach

Advanced GaN HEMT technology for millimetre-wave amplifiers

Gallium Nitride (GaN)-based High-Electron-Mobility Transistor (HEMT) technology is a breakthrough innovation in the semiconductor industry, offering high-frequency and high-power performance capabilities. GaN HEMTs are widely used in power electronics, wireless communication systems, and radar applications over the past two decades. The key advantages of GaN HEMTs to produce heterojunctions to larger bandgap materials Aluminium Gallium Nitride (AlGaN) and the heterostructure results in the formation of the 2- dimensional electron gas (2DEG) which exhibits high electron mobilities of upto 2000 cm²/V.s and high saturation velocity of 2×10⁷ cm/s, resulting in high switching speeds and power densities. Due to its wide bandgap of 3.4 eV, it also allows exceptionally high breakdown fields of 3.3 MV/cm. In this thesis, the focus is on the major challenges in the development of GaN HEMT technology including achieving a low resistance ohmic contact, reducing self-heating, and improving device high frequency performance. Due to the wide bandgap of III-nitride semiconductors, achieving low-resistance Ohmic contact resistance is difficult. Recessing the Ohmic region prior to metallization is a typical approach to lowering the contact resistance. The contact resistance is often minimised by optimising factors such as recess depth, anneal temperature, and metal stack design. In this work, the three approaches involving the recessing of the ohmic region were evaluated. The Ohmic contact area was recessed in patterns similar to a chess board, vertical recessed stripes, and horizontal recessed strips. The two different recess etch depths, shallow and deep etch depths of 9 nm and 30 nm, respectively, were investigate. The lowest contact resistance of 0.32 Ω.mm (compared to 0.59 Ω.mm for a conventional non-recessed Ohmic contact) was observed for a deep horizontal patterned structure. The results also indicate that a highly reproducible process. The other major issue to address was to reduce the impact of device self-heating by effective heat distribution and dissipation. A novel thermal management technique was proposed, and the preliminary results are promising. It exploits the very thin epitaxial layer stack of a buffer-less GaN-on-SiC HEMT structure. III-V nitride material is etched and removed from around the active device area and the Au bond pad electrodes sit directly on the SiC substrate, providing a route for thermal dissipation from the active device to the substrate. This approach was demonstrated to reduce device self-heating and to improve the current density of the device. We fabricated and compared the performance of devices fabricated on the buffer-free and conventional GaN HEMTs. For identically sized 2-μm gate long, two-finger 2 × 50 μm gate width device with a gate to drain spacing of 3 m, the conventional devices broke down at 186 V while for the buffer-free structure, it was over 200 V (above the measurement capability of our equipment). The maximum drain current density of ~631 mA/mm and ~ 686 mA/mm biased at VGS = 1 V for the two-finger 2 × 50 μm gate wide for buffer free and conventional GaN structure, respectively. The buffer free and conventional GaN structure devices were measured to determine their maximum cut-off frequency (fT) and maximum oscillation frequency (fmax) when biased at VDS = 15V. The lower gate leakage currents were observed for the fabricated buffer-free AlGaN/GaN HEMT device as compared to conventional GaN HEMTs 197μA and 260μA, respectively. Also, the buffer free device, which had two fingers each measuring 2x200 μm, yielded measurements of 4.6 GHz for fT and 9.8 GHz for fmax. The conventional GaN device, also with two fingers each measuring 2x200 μm, was tested and resulted in measurements of 6.3 GHz for fT and 14.7 GHz for fmax. These results demonstrate the high quality of the buffer-free GaN heterostructure despite the absence of thick transition layers as currently used in the conventional GaN HEMTs. This indicates that the "buffer-free" design has the potential to be useful for millimetre wave applications in the future. This thesis also describes the fabrication and characterisation of a 100 nm footprint Ni/Au-based T-gate HEMT, 2x25 μm gate width, 1.5 μm drain source spacing, 100nm Si₃N₄ passivation layer thickness and device exhibit quite high peak currents of 805mA/mm and peak transconductance value of 246 mS/mm due to the low thermal boundary resistance on this buffer free epilayer wafer. The breakdown voltage was measured 47 Volts. Yielding a cut-off frequency fT of 87 GHz and maximum oscillation frequency fₘₐₓ of 143 GHz. We have developed a method for fabricating a T-shaped gate for sub 100nm gate foot length. The 100 nm length results in robustness, repeatable and has a high yield. Our findings indicate that this gate design could be beneficial for AlGaN/GaN buffer-free HEMTs used in millimetre wave frequency applications

Buffer Related Dispersive Effects in Microwave GaN HEMTs

In applications such as mobile communication and radar, microwave power generation at high frequency is of utmost importance. The GaN HEMT offers a unique set of properties that makes it suitable for high power amplification at high frequencies. However, their performance is limited by trap states, leading to reduced output power and time variant effects. Furthermore, for good high frequency performance a high efficiency it is essential to limit the access resistances in the transistor. The GaN HEMT technology has long lacked a good ohmic contact with good reproducibility.\ua0In this thesis, three buffer designs are considered; C-doped GaN, AlGaN back barriers and a thin GaN structure. The three designs are evaluated in terms of trapping effects using the drain current transient technique. For the C-doped GaN buffer, trapping at dislocations covered with C-clusters is believed to be the main factor limiting output power. Dislocations are presumed to play a major role for the trapping behavior of AlGaN back barriers and the thin structure as well. The maximum output powers for C-doped GaN, AlGaN back barriers and the thin structure are 3.3, 2.7, and 3.9 W/mm at 30 GHz. The output power is found to be limited by trapping effects for all buffer designs. Moreover, a Ta-based, recessed ohmic contact enables a contact resistance of down to 0.14 Ωmm. The results also indicate that a highly reproducible process might be possible for deeply recessed contacts. An optimized AlGaN/GaN interface shows high mobility \textgreater2000 cm2/Vs without the use of an AlN-exclusion layer. The improved interface also decreases trapping effects and the gate-source capacitance at large electric fields compared to an unoptimized interface

AlGaN/GaN-based power semiconductor switches

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 209-219).AlGaN/GaN-based high-electron-mobility transistors (HEMTs) have great potential for their use as high efficiency and high speed power semiconductor switches, thanks to their high breakdown electric field, mobility and charge density. The ability to grow these devices on large-diameter Si wafers also reduces device cost and makes them easier for wide market adoption. However, the development of AlGaN/GaN-based power switches has encountered three major obstacles: the limited breakdown voltage of AlGaN/GaN transistors grown on Si substrates; the low performance of normally-off AlGaN/GaN transistors; and the degradation of device performance under high voltage pulsed conditions. This thesis studies these issues and presents new approaches to address these obstacles. The first part of the thesis studies the breakdown mechanism in AlGaN/GaN-on-Si transistors. A new quantitative model-trap-limited space-charge impact-ionization model- is developed. Based on this model, a set of design rules is proposed to improve the breakdown voltage of AlGaN/GaN-on-Si transistors. New technologies have also been demonstrated to increase the breakdown voltage of AlGaN/GaN-on-Si transistors beyond 1500 V. The second part of the thesis presents three technologies to improve the performance of normally-off AlGaN/GaN transistors. First, a dual-gate normally-off MISFET achieved high threshold voltage, high current and high breakdown voltage simultaneously by using an integrated cascode structure. Second, a tri-gate AlGaN/GaN MISFET demonstrated the highest current on/off ratio in normally-off GaN transistors with the enhanced electrostatic control from a tri-gate structure. Finally, a new etch-stop barrier structure is designed to address low channel mobility, high interface density and non-uniformity issues associated with the conventional gate recess technology. Using this new structure, normally-off MISFETs demonstrated high uniformity, steep sub-threshold slope and a record channel effective mobility. The thesis concludes with a new dynamic on-resistance measurement technique. With this method, the hard- and soft-switching characteristics of GaN transistors were measured for the first time.by Bin Lu.Ph.D