Reusing RTL assertion checkers for verification of SystemC TLM models

The recent trend towards system-level design gives rise to new challenges for reusing existing RTL intellectual properties (IPs) and their verification environment in TLM. While techniques and tools to abstract RTL IPs into TLM models have begun to appear, the problem of reusing, at TLM, a verification environment originally developed for an RTL IP is still under-explored, particularly when ABV is adopted. Some frameworks have been proposed to deal with ABV at TLM, but they assume a top-down design and verification flow, where assertions are defined ex-novo at TLM level. In contrast, the reuse of existing assertions in an RTL-to-TLM bottom-up design flow has not been analyzed yet, except by using transactors to create a mixed simulation between the TLM design and the RTL checkers corresponding to the assertions. However, the use of transactors may lead to longer verification time due to the need of developing and verifying the transactors themselves. Moreover, the simulation time is negatively affected by the presence of transactors, which slow down the simulation at the speed of the slowest parts (i.e., RTL checkers). This article proposes an alternative methodology that does not require transactors for reusing assertions, originally defined for a given RTL IP, in order to verify the corresponding TLM model. Experimental results have been conducted on benchmarks with different characteristics and complexity to show the applicability and the efficacy of the proposed methodology

Automated Hardware Prototyping for 3D Network on Chips

Vor mehr als 50 Jahren stellte Intel® Mitbegründer Gordon Moore eine Prognose zum Entwicklungsprozess der Transistortechnologie auf. Er prognostizierte, dass sich die Zahl der Transistoren in integrierten Schaltungen alle zwei Jahre verdoppeln wird. Seine Aussage ist immer noch gültig, aber ein Ende von Moores Gesetz ist in Sicht. Mit dem Ende von Moore’s Gesetz müssen neue Aspekte untersucht werden, um weiterhin die Leistung von integrierten Schaltungen zu steigern. Zwei mögliche Ansätze für "More than Moore” sind 3D-Integrationsverfahren und heterogene Systeme. Gleichzeitig entwickelt sich ein Trend hin zu Multi-Core Prozessoren, basierend auf Networks on chips (NoCs). Neben dem Ende des Mooreschen Gesetzes ergeben sich bei immer kleiner werdenden Technologiegrößen, vor allem jenseits der 60 nm, neue Herausforderungen. Eine Schwierigkeit ist die Wärmeableitung in großskalierten integrierten Schaltkreisen und die daraus resultierende Überhitzung des Chips. Um diesem Problem in modernen Multi-Core Architekturen zu begegnen, muss auch die Verlustleistung der Netzwerkressourcen stark reduziert werden. Diese Arbeit umfasst eine durch Hardware gesteuerte Kombination aus Frequenzskalierung und Power Gating für 3D On-Chip Netzwerke, einschließlich eines FPGA Prototypen. Dafür wurde ein Takt-synchrones 2D Netzwerk auf ein dreidimensionales asynchrones Netzwerk mit mehreren Frequenzbereichen erweitert. Zusätzlich wurde ein skalierbares Online-Power-Management System mit geringem Ressourcenaufwand entwickelt. Die Verifikation neuer Hardwarekomponenten ist einer der zeitaufwendigsten Schritte im Entwicklungsprozess hochintegrierter digitaler Schaltkreise. Um diese Aufgabe zu beschleunigen und um eine parallele Softwareentwicklung zu ermöglichen, wurde im Rahmen dieser Arbeit ein automatisiertes und benutzerfreundliches Tool für den Entwurf neuer Hardware Projekte entwickelt. Eine grafische Benutzeroberfläche zum Erstellen des gesamten Designablaufs, vom Erstellen der Architektur, Parameter Deklaration, Simulation, Synthese und Test ist Teil dieses Werkzeugs. Zudem stellt die Größe der Architektur für die Erstellung eines Prototypen eine besondere Herausforderung dar. Frühere Arbeiten haben es versäumt, eine schnelles und unkompliziertes Prototyping, insbesondere von Architekturen mit mehr als 50 Prozessorkernen, zu realisieren. Diese Arbeit umfasst eine Design Space Exploration und FPGA-basierte Prototypen von verschiedenen 3D-NoC Implementierungen mit mehr als 80 Prozessoren

High-level synthesis for FPGAs: From prototyping to deployment

Abstract-Escalating System-on-Chip design complexity is pushing the design community to raise the level of abstraction beyond RTL. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS methodology is happening now, especially for FPGA designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. Index Terms-Domain-specific design, field-programmable gate array (FPGA), high-level synthesis (HLS), quality of results (QoR)

A Middleware-centric design methodology for networked embedded systems

Negli ultimi anni \ue8 incrementato considerevolmente l\u2019interesse verso gli \u201dambient intelligence\u201d, sistemi informatici, tipicamente composti da \u201dnetworked embedded systems\u201d (Wirelesse sensor networks, mobile terminal, PDA, etc.) i quali sono integrati nell\u2019ambiente umano con l\u2019obiettivo di migliorare la qualit`a della vita nel modo pi naturale possibile. Una applicazione \u201dNetworked Embedded System\u201d (NES) \ue8 un\u2019applicazione distribuita, eseguita su piattaforme HW/SW eterogenee che interagiscono attraverso differenti canali di comunicazione. Generalmente queste applicazioni per dispositivi NES vengono sviluppate senza il supporto di software di sistema, obbligando il progettista a modellare queste applicazioni utilizzando direttamente le primitive fornite dal sistema operativo embedded o le API dei drivers dei dispositivi HW. Con questa metodologia di progettazione, le applicazioni per sistemi embedded vengono realizzate ad-hoc per la piattaforma HW/SW, risultando essere n\ue9 portabili, n\ue9 scalabili e di conseguenza particolarmente costose. A causa di questi problemi, negli ultimi anni si \ue8 adottato un flusso di progettazione che prevede l\u2019introduzione di un \u201dservice layer\u201d chiamato middleware, il quale astrae le peculiarit del sistema operativo e dei componenti HW, semplificando la progettazione di queste applicazioni embedded. Allo stato dell\u2019arte sono presenti molte implmentazioni di middleware con differenti paradigmi di programmazione, e la scelta di quale utilizzare per progettazione una applicazione NES basata sui seguenti criteri: \u2022 abilit`a/conoscenza/capacit`a di programmazione da parte del progettista; \u2022 piattaforma HW/SW disponinile. Gli svantaggi di questo approccio sono un pi\uf9 complesso flusso di progettazione legato alla mancanza di portabilit\ue0 della stessa applicazione su differenti dispositivi embedded. Questo significa che la presenza del middleware non \ue8 mai stata introdotta nel flusso di progettazione come una esplicita dimensione di progetto. Obiettivo della tesi di dottorato \ue8 lo studio e la realizzazione di un flusso di progettazione per applicazioni per NES, dove il middleware \ue8 una dimensione di progetto, diventando una variabile di progetto come lo sono il software e lo hardware. Questo punto \ue8 ottenuto risolvendo tre problemi: \u2022 Fornire un modello di middleware astratto il quale pu\uf2 essere usato come componente del flusso di progettazione; questo middleware astratto, chiamato Abstract Middleware Services (AMS), fornisce un insieme di servizi astratti basati su differenti paradigmi di programmazione dei middleware reali. Utilizzando questo modello di middleware stratto, il progettista \ue8 facilitato nello sviluppo delle applicazioni per NES. \u2022 Fornire un ambiente di simulazione dove validare e simulare l\u2019intero modello realizzato dal progettista. \u2022 Fornire una metodologia automatica di traduzione da AMS ad un middleware reale, per poter eseguire l\u2019applicazione su una reale piattaforma HW/SW, dotata di un middleware qualsiasi. L\u2019attivit di dototrato ha permesso la definizione di un nuovo approccio di progettazione basato su un modello di middleware astratto che fornisce un ambiente per la modellazione e la validazione di applicazioni per Networked Embedded Systems, risolvendo i tre punti precedenti. Inoltre, al fine di produrre un efficiente ambiente di simulazione e modellazione, sono state analizzate le metodologie di co-simulazione hardware-software-network attualmente presenti in letteratura. L\u2019attivit\ue0 di dottorato inoltre parte integrante del progetto ANGEL finanziato dalla Comunit\ue0 Europea (IST-2005-33506 - Embedded Systems), il cui obiettivo \ue8 lo sviluppo di una piattaforma per la realizzazione di sistemi eterogenei nei quali Wireless Sensor Network (WSN) e tradizionali reti di comunicazioni cooperano per monitorare e migliorare la qualit\ue0 della vita in habitat comuni. Durante questa attivit\ue0 il flusso di progettazione che include anche il middleware come variabile di progetto, oggetto della tesi di dottorato, sar esemplificato su WSN e terminali mobili (per esempio cellulari) per far si che questi possano dialogare tra loro in modo intelligente.Ambient intelligence, pervasive and ubiquitous computing are the center of a great deal of attention because of their promise to bring benefits for end-users, higher revenues for manufacturers and new challenges for researchers. Typical computing technologies (such as telemedicine, manufacturing, crisis management) are part of a broader class of Networked Embedded Systems (NES) in which a large number of nodes are connected together and collaborate to perform a common task under a defined set of constraints. Therefore, the key aspects of these applications are their distributed nature and the presence of very limited HW resources, as in case of WSNs. Their wide adoption requires interoperability across different manufacturers, simplification of application development, simulation tools for functional validation and the fulfilment of tight HW/SW constraints. Interoperability is achieved through the use of standard protocol stacks (e.g., IEEE 802.15.1/Bluetooth and IEEE 802.15.4/Zig- Bee). Simplification of application development can be achieved through a service layer, named middleware, which abstracts from the peculiarities of the operating system and HW components. Traditionally, many NES applications have been developed without support from system software [1] excepts for device drivers and operating systems. State-of-the-art techniques [2] for NES focus on simple data-gathering applications, and in most cases, the design of the application and the system software are usually closely-coupled, or even combined as a monolithic procedure. Such applications are neither flexible nor scalable and they should be re-written if the platform changes. Middleware is emerging as an important architectural component in supporting NES applications able to facilitate the application development. The role of middleware is to present a unified programmingmodel to application designers and to mask out the problems of heterogeneity and distribution providing a basic set of tools and libraries for the low-level handling of technology-specific NES. Several NES middleware have been implemented in the past years each one providing different programming paradigms (e.g., Tuplespace, messageoriented, object-oriented, database, etc.) and differ with respect to ease to use, expressiveness, scalability and overhead. However, their diversity makes the development of high quality middleware-centric software systems complex: software engineering methods and tools should be developed with the use of middleware in mind. In such way, Sensation [xxx] presents a middleware platform solution for pervasive applications inWSN providing a developer-friendly programming interface. This approach is valid just for WSN and does not include a network simulator for an exhaustive network evaluation. Model Driven Architecture (MDA) tries to overcome this problem; MDA is a new way of writing specifications, based on a platform-independent model. A complete MDA specification consists of a platform-independent UML model, one or more platform-specific models, and interface definitions, each describing how the base model is implemented on a different middleware platform. The MDA focuses primarily on the functionality and behaviour of a distributed application or system, not on the technology in which it will be implemented. Furthermore,MDA does not directly provide a simulation environment. Simulation tools are used for validating the application: there is a range of NES simulators available that focus on the network itself. NS-2 is a pure network simulator tool, where the nodes are abstracted and do not run real codes or operating systems, but rather simple behavioral models or statistical traffic generators. The advantage of NS-2 is that scalability is excellent. TOSSIM is a platform-specific simulator environment for sensor networks based on TinyOs operating system. TOSSIM can compile unchanged TinyOS applications directly into its framework, which means that most of the codes written for TOSSIM can be directly used in TinyOS. TOSSIM is a specific simulator for TinyOS and Berkeley motes and cant be used for simulating a generic NES (e.g.,WSN). Finally, SIMICS is a commercial full-system simulator that can be used to simulate heterogenous networked and distributed systems. Complete SW stacks from real system can run on the simulator without any modification. Despite of these punctual contributions, the literature does not report a complete design methodology for NES applications integrating all such three aspects. Therefore, in order to fully support the applications of a great variety of users with different needs, a complete NES application modelling and simulation environment have to include two main components: \u2022 a simulator to validate and explore application functional behaviuor in a network simulated environment supporting interoperability between different implementation platforms and ensure scalability of the NES technology. \u2022 a middleware environemnt providing different programming paradigms. This Layer will serve as an abstraction layer hiding the different NES implementations peculiarities from end-user applications. The goal of this work is to present a middleware-centric design flow for NES, where the middleware plays a decisive role in the design process. The proposed methodology allows programmers to write NES applications by using the system description language named SystemC and the AbstractMiddleware Environment (AME) framework for fast simulation. This proposal has three main advantages: (1) It provides a set of abstract services supporting the programming paradigms of different actual middleware implementations in order to meet the skills of the designer. AME facilitates the NES design flow by providing a unified and developer-common interface concealing the peculiarities of the underlying NES where the simulation environment is modelled in order to simulate the NES applications taking in account hardware and network effects. (2) The application can be simulated at early stage of the design flow for functional validation. (3) automatic mapping of AME applications on the actual platform; this guarantees the correct trade-off between level of abstraction and efficiency of implementation. In the follow we classify the actual middleware approaches according to their programming paradigms; then the AMEcentric design flow is described and finally we report the experimental results

Towards a tighter integration of generated and custom-made hardware

Most of today's high-level synthesis tools offer a fixed set of interfaces to communicate with the outer world. A direct integration of custom IF in the datapath would often be more beneficial than an integration using such communication interfaces. If a certain interface protocol is not offered by the tool, either translation blocks (wrappers) are needed or the code should be written at a lower level. The former solution may hurt the performance, while the latter one is often impossible using an untimed high-level description. In this paper interface protocols or sets of JP core accesses are first described at a low level as sets of operations with scheduling information (macros). During the synthesis process, corresponding function calls are mapped to these macros. This facilitates the integration of custom-made hardware and hardware generated by high-level synthesis tools

Dynamic Assertion-Based Verification for SystemC

SystemC has emerged as a de facto standard modeling language for hardware and embedded systems. However, the current standard does not provide support for temporal specifications. Specifically, SystemC lacks a mechanism for sampling the state of the model at different types of temporal resolutions, for observing the internal state of modules, and for integrating monitors efficiently into the model's execution. This work presents a novel framework for specifying and efficiently monitoring temporal assertions of SystemC models that removes these restrictions. This work introduces new specification language primitives that (1) expose the inner state of the SystemC kernel in a principled way, (2) allow for very fine control over the temporal resolution, and (3) allow sampling at arbitrary locations in the user code. An efficient modular monitoring framework presented here allows the integration of monitors into the execution of the model, while at the same time incurring low overhead and allowing for easy adoption. Instrumentation of the user code is automated using Aspect-Oriented Programming techniques, thereby allowing the integration of user-code-level sample points into the monitoring framework. While most related approaches optimize the size of the monitors, this work focuses on minimizing the runtime overhead of the monitors. Different encoding configurations are identified and evaluated empirically using monitors synthesized from a large benchmark of random and pattern temporal specifications. The framework and approaches described in this dissertation allow the adoption of assertion-based verification for SystemC models written using various levels of abstraction, from system level to register-transfer level. An advantage of this work is that many existing specification languages call be adopted to use the specification primitives described here, and the framework can easily be integrated into existing implementations of SystemC