Determination of key device parameters for short- and long-channel Schottky-type carbon nanotube field-effect transistors

The Schottky barrier, contact resistance and carrier mobility in carbon nanotube (CNT) field-effect transistors (FETs) are discussed in detail in this thesis. Novel extraction methods and definitions are proposed for these parameters. A technology comparison with other emerging transistor technologies and a performance projection study are also presented. A Schottky barrier height extraction method for CNTFETs considering one-dimensional (1D) conditions is developed. The methodology is applied to simulation and experimental data of CNTFETs feasible for manufacturing. Y-function-based methods (YFMs) have been applied to simulation and experimental data in order to extract a contact resistance for CNTFETs. Both extraction methods are more efficient and accurate than other conventional approaches. Practical mobility expressions are derived for CNTFETs covering the ballistic as well as the non-ballistic transport regime which enable a straightforward evaluation of the transport in CNTs. They have been applied to simulation and experimental data of devices with different channel lengths and Schottky barrier heights. A comparison of fabricated emerging transistors based on similar criteria for various application scenarios reveals CNTFETs as promising candidates to compete with Si-based technologies in low-power static and dynamic applications. A performance projection study is suggested for specific applications in terms of the studied design parameters

Modelling of field-effect transistors based on 2D materials targeting high-frequency applications

New technologies are necessary for the unprecedented expansion of connectivity and communications in the modern technological society. The specific needs of wireless communication systems in 5G and beyond, as well as devices for the future deployment of Internet of Things has caused that the International Technology Roadmap for Semiconductors, which is the strategic planning document of the semiconductor industry, considered since 2011, graphene and related materials (GRMs) as promising candidates for the future of electronics. Graphene, a one-atom-thick of carbon, is a promising material for high-frequency applications due to its intrinsic superior carrier mobility and very high saturation velocity. These exceptional carrier transport properties suggest that GRM-based field-effect transistors could potentially outperform other technologies. This thesis presents a body of work on the modelling, performance prediction and simulation of GRM-based field-effect transistors and circuits. The main goal of this work is to provide models and tools to ease the following issues: (i) gaining technological control of single layer and bilayer graphene devices and, more generally, devices based on 2D materials, (ii) assessment of radio-frequency (RF) performance and microwave stability, (iii) benchmarking against other existing technologies, (iv) providing guidance for device and circuit design, (v) simulation of circuits formed by GRM-based transistors.Comment: Thesis, 164 pages, http://hdl.handle.net/10803/40531

Modelling Graphene Field-Effect Transistors

Today, transistors with 20 nanometer (nm) channel length are in mass production and many researchers believe that we are reaching a limit with downsizing conventionally used silicon metal-oxide-semiconductor field-effect transistors (MOSFETs) [1]. To keep up with the trend of making the transistor smaller, new channel materials are studied, and graphene has come into the spotlight. Graphene became a serious contender mostly due to its high mobility, but other properties such as high velocity saturation and the two-dimensional (2D) nature of the material have gained more attention in recent years [2–4]. The first graphene field-effect transistor (GFET) was reported in 2004, since many transistors with graphene as a channel material have been successfully fabricated [3]. It is important to have accurate simulation models that showcase all the peculiar behaviours of GFETs. Even though several new models with high accuracy, have been presented in recent years, few theoretical explanations exist. This thesis work focuses greatly on the theory behind two different simulation models for GFETs. Several parameter approximations are investigated, with focus on the possibility of showcasing negative differential resistance (NDR). In conclusion, we can see that the drift-diffusion (DD) model show good agreement with data and showcases NDR, while the virtual source (VS) model is more unstable and does not give NDR. I hope this thesis can act as a knowledge base, to facilitate for future simulation models.Transistor av materialet grafen. En av världens största uppfinningar är också den minsta av dom alla. Transistorn storlek är endast 1/5000 av ett hårstrå. Men låt inte detta lura er, tack vare denna smarta uppfinning utför din mobil mer och mer avancerade uppgifter. Transistorn sägs vara en av de största uppfinningarna i modern historia. Uppfinningen har nämnts i samma klass som bilen och telefonen. Idag finns transistorn i nästan all modern elektronik, vilket inte är så chockerande då 2 913 276 327 576 980 000 000 stycken transistorer har tillverkats industriellt sedan 1947 [5]. Siffran blir inte mer greppbar bara för att man ser hur många transistorer det är per person på jorden; 388 436 843 677 stycken transistorer per person. Trots detta, är inte transistorn något som diskuteras i vardagliga sammanhang. Så vad är en transistor? Enkelt uttryckt så är det en elektronikkomponent, som kan efterliknas vid en ventil. Vanligtvis har transistorn tre terminaler, vid varje terminal kan spänningen regleras. Beroende på spänningsstyrkorna ändras strömsignalen genom komponenten. Har du märkt att våra tv-apparater, datorer och telefoner tycks bli mindre, lättare och smidigare trots att de har högre prestanda, kan lagra mer information och arbetar snabbare? Detta är till stor del tack vare utvecklingen av transistorerna. Idag finns det transistorer så små som 20 nanometer (nm) i massproduktion [3]. Okej, tänker du då, hur stort är 20 nm? Det är en mycket bra fråga, som inte är helt enkel att svara på. Generellt brukar man säga att ett hårstrå på ditt huvud är 0.1 mm, det betyder att 20 nm endast är 1/5000 av ett hårstrå. Transistorerna vi tillverkar idag är med andra ord otroligt små. De flesta transistorer som används idag görs av Kisel. Men när dessa ska tillverkas så små som 20 nm börjar det bli problem med materialet Kisel. Det blir läckage och oönskade kapacitanser som gör att mer energi krävs för att få önskad effekt. Forskare behövde därför fundera på om det är möjligt att byta ut Kisel mot något bättre material. Materialet grafen kom upp som tänkbar ersättare. Grafen är gjort av Kol-atomer och är ett otroligt starkt material. Materialet är dessutom bättre än någon metall på att leda ström. I denna rapport tittar jag närmare på speciella egenskaper hos grafen. Jag går sedan vidare till teorin bakom grafen-transistorer, här beskriver jag vad som händer när man ändrar spänningen vid de olika terminalerna. Jag har skapat visuella bilder för att se vad som händer inne i transistorn. Till sist, beskriver jag hur man kan skapa en matematisk modell som beskriver strömmen som går genom grafen-transistorn. Målet med mitt arbete var att på ett grundläggande sätt förklara teorin bakom de matematiska modellerna för grafen-transistorer. Ofta måste förenklingar göras då det är svårt att beskriva allt i en transistor matematiskt. Jag har undersökt vad tidigare forskare har gjort och jämfört olika förenklingar samt hur dessa påverkar strömsignalen

Miniaturized Transistors

What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

Electronic Nanodevices

The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor

Hybrid Nanomaterials

Two of the hottest research topics today are hybrid nanomaterials and flexible electronics. As such, this book covers both topics with chapters written by experts from across the globe. Chapters address hybrid nanomaterials, electronic transport in black phosphorus, three-dimensional nanocarbon hybrids, hybrid ion exchangers, pressure-sensitive adhesives for flexible electronics, simulation and modeling of transistors, smart manufacturing technologies, and inorganic semiconductors

Graphene Transistor-Based Printable Electronics for Wearable Biosensing Applications

Graphene field-effect transistor (GFET) is becoming an increasingly popular biosensing platform for monitoring health conditions through biomarker detection. Moreover, the graphene’s 2-dimensional geometry makes it ideal for implementing flexible or wearable electronic devices. By using a GFET platform as a biosensor, users can easily monitor numerous health conditions. A sweat-based biosensor can non-invasively monitor levels of proteins in the body and alert the user to possible issues such as a steep increase or decrease in a particular protein. By creating a platform that can be used as a wearable biosensor, it allows for rapid results and a cheaper way to provide clinical quality data about one’s health conditions. This thesis presents a novel approach for creating a low cost, reliable and selective, wearable biosensor for real-time observation and tracking of the levels of the protein biomarker Interleukin-6 (IL-6). A printable graphene transistor-based biosensor is created by using a PCB printer on a flexible Kapton substrate. The conductive channel of the GFET is created using a chemical vapor deposition (CVD)-grown graphene layer. By functionalizing (or modifying) the graphene surface with biorecognition elements such as antibodies or aptamers in the channel of the device, the GFET can operate as a biosensor. When various levels of IL-6 were introduced into the GFET device, the target proteins bind to the aptamers causing a change in the charge carrier concentration. The device is able to monitor in real-time the levels of IL-6 by observing the drain-to-source current of the GFET which correlates to the IL-6 concentration being measured. The device implemented contains an integrated current meter which is one of the building blocks for creating a wearable electronic biosensor

Toward Real Setting Applications of Organic and Perovskite Solar Cells: A Comparative Review

The development of efficient, reliable, and clean energy sources is one of the global priorities for enabling a sustainable transition toward a green society and economy. The third‐generation solar cells, such as organic solar cells (OSCs) and perovskite solar cells (PSCs), are among the most promising platforms for the generation of electrical power from sunlight for a wide range of applications. However, the widespread diffusion of emerging photovoltaics technologies is hampered by issues occurring in the translation of laboratory‐scale R&D efforts to real settings. Herein, starting from a thorough survey of latest research on OSC and PSC technologies, critical factors related to fabrication and operation of solar cells, especially in terms of materials properties/requirements and beyond metrics built on efficiency only, are analyzed. On this basis, OSCs and PSCs are compared in terms of their potential in real application scenarios, also highlighting their peculiarities in view of their future large‐scale utilization