Design of Fully-Integrated High-Resolution Radars in CMOS and BiCMOS Technologies

The RADAR, acronym that stands for RAdio Detection And ranging, is a device that uses electromagnetic waves to detect the presence and the distance of an illuminated target. The idea of such a system was presented in the early 1900s to determine the presence of ships. Later on, with the approach of World War II, the radar gained the interest of the army who decided to use it for defense purposes, in order to detect the presence, the distance and the speed of ships, planes and even tanks. Nowadays, the use of similar systems is extended outside the military area. Common applications span from weather surveillance to Earth composition mapping and from flight control to vehicle speed monitoring. Moreover, the introduction of new ultrawideband (UWB) technologies makes it possible to perform radar imaging which can be successfully used in the automotive or medical field. The existence of a plenty of known applications is the reason behind the choice of the topic of this thesis, which is the design of fully-integrated high-resolution radars. The first part of this work gives a brief introduction on high resolution radars and describes its working principle in a mathematical way. Then it gives a comparison between the existing radar types and motivates the choice of an integrated solution instead of a discrete one. The second part concerns the analysis and design of two CMOS high-resolution radar prototypes tailored for the early detection of the breast cancer. This part begins with an explanation of the motivations behind this project. Then it gives a thorough system analysis which indicates the best radar architecture in presence of impairments and dictates all the electrical system specifications. Afterwards, it describes in depth each block of the transceivers with particular emphasis on the local oscillator (LO) generation system which is the most critical block of the designs. Finally, the last section of this part presents the measurement results. In particular, it shows that the designed radar operates over 3 octaves from 2 to 16GHz, has a conversion gain of 36dB, a flicker-noise-corner of 30Hz and a dynamic range of 107dB. These characteristics turn into a resolution of 3mm inside the body, more than enough to detect even the smallest tumor. The third and last part of this thesis focuses on the analysis and design of some important building blocks for phased-array radars, including phase shifter (PHS), true time delay (TTD) and power combiner. This part begins with an exhaustive introduction on phased array systems followed by a detailed description of each proposed lumped-element block. The main features of each block is the very low insertion loss, the wideband characteristic and the low area consumption. Finally, the major effects of circuit parasitics are described followed by simulation and measurement results

OFDM para distribuição de dados de controlo em phased array antenas

Mestrado em Engenharia Eletrónica e TelecomunicaçõesCurrently, all the control data behind the RF front-end modules in phased array radars is transmitted digitally and simultaneously by means of optical ber, resulting in a massive distribution network. The design of cheaper radars requires alternative ways of transmission to be explored. An intuitive and rather straight approach is to take advantage of the already existent RF layer used for the distribution of the radar pulse. The aim of this thesis work is to investigate OFDM as a modulation option for that approach and to determine whether or not it is a viable one. As proof of concept, experimental results are presented and discussed.Actualmente, toda a informa cão de controlo por detráas dos móodulos T/R (Transmit/ Receive) em radares com phased arrays e transmitida digital e simultaneamente atrav és de fi bra optica, resultando numa rede de distribuiçaõ massiva. Para que se possa reduzir o custo de produção e limitações no design, e fundamental a exploração de alternativas para a transmissão destes dados. Uma ideia intuitiva e que não implica grandes modi ca ções estruturais, e tirar vantagem da j a existente layer de RF (R adio Frequência) usada para distribuição do pulso de radar pelos m ódulos. O objectivo desta tese é investigar OFDM (Orthogonal Frequency Division Multiplexing) como uma das opções para modulação do novo sinal de RF responsável pela informa ção de controlo e determinar se esta é ou não uma escolha vi ável. Como prova de conceito, resultados experimentais serão apresentados e discutidos

Ultra Low Power IEEE 802.15.4/ZIGBEE Compliant Transceiver

Low power wireless communications is the most demanding request among all wireless users. A battery life that can survive for years without being replaced, makes it realistic to implement many applications where the battery is unreachable (e.g. concrete walls) or expensive to change (e.g underground applications). IEEE 802.15.4/ZIGBEE standard is published to cover low power low cost applications, where the battery life can last for years, because of the 1% duty cycle of operation. A fully integrated 2.4GHz IEEE802.15.4 Compliant transceiver suitable for low power, low cost ZIGBEE applications is implemented. Direct conversion architecture is used in both Receiver and Transmitter, to achieve the minimum possible power and area. The chip is fabricated in a standard 0.18um CMOS technology. In the transmit mode, the transmitter chain (Modulator to PA) consumes 25mW, while in the receive mode, the iv receiver chain (LNA to Demodulator) consumes 5mW. The Integer-N Frequency Synthesizer consumes 8.5mW. Other Low power circuits are reported; A 13.56 Passive RFID tag and a low power ADC suitable for Built-In-Testing applications

Linear Operation of Switch-Mode Outphasing Power Amplifiers

Radio transceivers are playing an increasingly important role in modern society. The ”connected” lifestyle has been enabled by modern wireless communications. The demand that has been placed on current wireless and cellular infrastructure requires increased spectral efficiency however this has come at the cost of power efficiency. This work investigates methods of improving wireless transceiver efficiency by enabling more efficient power amplifier architectures, specifically examining the role of switch-mode power amplifiers in macro cell scenarios. Our research focuses on the mechanisms within outphasing power amplifiers which prevent linear amplification. From the analysis it was clear that high power non-linear effects are correctable with currently available techniques however non-linear effects around the zero crossing point are not. As a result signal processing techniques for suppressing and avoiding non-linear operation in low power regions are explored. A novel method of digital pre-distortion is presented, and conventional techniques for linearisation are adapted for the particular needs of the outphasing power amplifier. More unconventional signal processing techniques are presented to aid linearisation of the outphasing power amplifier, both zero crossing and bandwidth expansion reduction methods are designed to avoid operation in nonlinear regions of the amplifiers. In combination with digital pre-distortion the techniques will improve linearisation efforts on outphasing systems with dynamic range and bandwidth constraints respectively. Our collaboration with NXP provided access to a digital outphasing power amplifier, enabling empirical analysis of non-linear behaviour and comparative analysis of behavioural modelling and linearisation efforts. The collaboration resulted in a bench mark for linear wideband operation of a digital outphasing power amplifier. The complimentary linearisation techniques, bandwidth expansion reduction and zero crossing reduction have been evaluated in both simulated and practical outphasing test benches. Initial results are promising and indicate that the benefits they provide are not limited to the outphasing amplifier architecture alone. Overall this thesis presents innovative analysis of the distortion mechanisms of the outphasing power amplifier, highlighting the sensitivity of the system to environmental effects. Practical and novel linearisation techniques are presented, with a focus on enabling wide band operation for modern communications standards

Source-synchronous I/O Links using Adaptive Interface Training for High Bandwidth Applications

Mobility is the key to the global business which requires people to be always connected to a central server. With the exponential increase in smart phones, tablets, laptops, mobile traffic will soon reach in the range of Exabytes per month by 2018. Applications like video streaming, on-demand-video, online gaming, social media applications will further increase the traffic load. Future application scenarios, such as Smart Cities, Industry 4.0, Machine-to-Machine (M2M) communications bring the concepts of Internet of Things (IoT) which requires high-speed low power communication infrastructures. Scientific applications, such as space exploration, oil exploration also require computing speed in the range of Exaflops/s by 2018 which means TB/s bandwidth at each memory node. To achieve such bandwidth, Input/Output (I/O) link speed between two devices needs to be increased to GB/s. The data at high speed between devices can be transferred serially using complex Clock-Data-Recovery (CDR) I/O links or parallely using simple source-synchronous I/O links. Even though CDR is more efficient than the source-synchronous method for single I/O link, but to achieve TB/s bandwidth from a single device, additional I/O links will be required and the source-synchronous method will be more advantageous in terms of area and power requirements as additional I/O links do not require extra hardware resources. At high speed, there are several non-idealities (Supply noise, crosstalk, Inter- Symbol-Interference (ISI), etc.) which create unwanted skew problem among parallel source-synchronous I/O links. To solve these problems, adaptive trainings are used in time domain to synchronize parallel source-synchronous I/O links irrespective of these non-idealities. In this thesis, two novel adaptive training architectures for source-synchronous I/O links are discussed which require significantly less silicon area and power in comparison to state-of-the-art architectures. First novel adaptive architecture is based on the unit delay concept to synchronize two parallel clocks by adjusting the phase of one clock in only one direction. Second novel adaptive architecture concept consists of Phase Interpolator (PI)-based Phase Locked Loop (PLL) which can adjust the phase in both direction and achieve faster synchronization at the expense of added complexity. With an increase in parallel I/O links, clock skew which is generated by the improper clock tree, also affects the timing margin. Incorrect duty cycle further reduces the timing margin mainly in Double Data Rate (DDR) systems which are generally used to increase the bandwidth of a high-speed communication system. To solve clock skew and duty cycle problems, a novel clock tree buffering algorithm and a novel duty cycle corrector are described which further reduce the power consumption of a source-synchronous system

Unintentional Islanding in Distribution Networks with Large Penetration of Power Electronics and Renewable Energy Systems

The PhD thesis focus on the analysis and investigation of a crucial issue related to increasing number of distributed energy resources (DERs). This recent issue is the unintentional (i.e. uncontrolled) islanding operation in distribution network with large penetration of DERs based on power electronic converters. Particular focus has been addressed to the interaction between DERs, protection systems and new connection rules required by standard bodies. The aim of the research activity is the investigation on the causes and the influencing factors of unintentional islanding in medium and low voltage (MV and LV) distribution network. The unintentional islanding issue has interested many studies and publications over the last decades. However, the literature research is lacking of considering the lately introduced European standards and technical specifications for DERs. Therefore, during the PhD research, novel aspects of how requirements and ancillary services influence the unintentional islanding operations have been studied, highlighting novel relevant factors, such as the role of the loads characteristics, the influence of the frequency measure and the inverter regulation speed

Application of Fuzzy Logic for Performance Enhancement of Drives

Fuzzy logic shows enormous potential for advancing power electronics technology. Its application to DC and AC drives control is discussed here. Initially, a phase-controlled bridge converter DC drive was considered. Analysis of converter performance at continuous and discontinuous conduction modes was first conducted. Fuzzy control was used to linearize the transfer characteristics of the converter in discontinuous conduction mode. It was then extended to current and speed loops, replacing the conventional proportional-integral controllers. The control algorithms were developed in detail, and verified by PC-SIMNON (developed by Lund Institute of Technology Sweden) digital simulation. Significant performance improvement was achieved over conventional control methods. Efficiency optimization of an indirect vector controlled induction motor drive was next considered. An accurate loss model of the converter induction machine system was first developed. Steady-state fundamental and harmonics loss characteristics, besides the dynamic of the machine were analyzed and incorporated in the model, resulting in a new synchronous frame dynamic De-Qe equivalent circuit. The converter system has been modeled accurately for conduction and switching losses. The lossy models were then used in the validation of the fuzzy logic based on-line efficiency optimization control. At steady-state, the fuzzy controller adaptively changes the excitation current on the basis of measured input power, until the maximum efficiency point is reached. The pulsating torque, due to flux reduction, has been compensated by an ingenious feedforward scheme. During transients, rated flux is established, to get the best transient response. After a comprehensive simulation study, an experimental 5 hp drive system was tested, with the proposed controller implemented on a Texas Instrument TMS320C25 digital signal processor, and the theoretical development was fully validated. Finally, fuzzy logic was applied in combination with model-reference adaptive control (MRAC) technique to slip gain tuning of an indirect vector controlled induction motor drive. The MRAC methods based on reactive power and D-axis voltage were combined through a weighting factor, generated by a fuzzy controller, that ensures the use of the best method for any point in the torque-speed plane. A second fuzzy controller tunes the slip gain based on combined detuning error and its slope. The drive performance was extensively investigated through simulations and experiments. The results confirmed the validity of the proposed method

Advanced Trends in Wireless Communications

Physical limitations on wireless communication channels impose huge challenges to reliable communication. Bandwidth limitations, propagation loss, noise and interference make the wireless channel a narrow pipe that does not readily accommodate rapid flow of data. Thus, researches aim to design systems that are suitable to operate in such channels, in order to have high performance quality of service. Also, the mobility of the communication systems requires further investigations to reduce the complexity and the power consumption of the receiver. This book aims to provide highlights of the current research in the field of wireless communications. The subjects discussed are very valuable to communication researchers rather than researchers in the wireless related areas. The book chapters cover a wide range of wireless communication topics

Analogue filter networks: developments in theory, design and analyses

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