Dependability-Assured Software Transformation

The proposed research is to create new paradigm of software transformation and analysis tools that will incorporate computer-aided prototyping system (CAPS) into dependability-assured software transformational platform (DAST) for highly dependable embedded systems (HDES). DAST extends CAPS with software architecting and composition technologies to transform macro dependability (global qualitative requirements) into micro dependability (quantitative constraints). Based upon rapid prototyping, the dependability-assured transformational process from a rapid-prototyped system to the highly dependable embedded system will involve quantitative constraint abstraction in multiple perspectives, software transformation, and formal method applied to verify the correctness of the eventual-evolved system.NSFApproved for public release; distribution is unlimited

Formalization and Correctness of the PALS Architectural Pattern for Distributed Real-Time Systems

Many Distributed Real-Time Systems (DRTS), such as integrated modular avionics systems and distributed control systems in motor vehicles, are made up of a collection of components communicating asynchronously among themselves and with their environment that must change their state and respond to environment inputs within hard real-time bounds. Such systems are often safety-critical and need to be certi???ed; but their certi???cation is currently very hard due to their distributed nature. The Physically Asynchronous Logically Synchronous (PALS) architectural pattern can greatly reduce the design and veri???cation complexities of achieving virtual synchrony in a DTRS. This work presents a formal speci???cation of PALS as a formal model transformation that maps a synchronous design, together with a set of performance bounds of the underlying infrastructure, to a formal DRTS speci???cation that is semantically equivalent to the synchronous design. This semantic equivalence is proved, showing that the formal veri???cation of temporal logic properties of the DRTS can be reduced to their veri???cation on the much simpler synchronous design. An avionics system case study is used to illustrate the usefulness of PALS for formal verification purposes.unpublishednot peer reviewe

A Reactive and Cycle-True IP Emulator for MPSoC Exploration

The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bitand cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (tasksynchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context

An Interactive System Level Simulation Environment for Systems- on-Chip

International audienceThis article presents an interactive simulation environment for high level models intended for Design Space Exploration of Systems-On-Chip. The existing open source development environment TTool supports the MARTE compliant UML profile DIPLODOCUS and enables the designer to create, simulate and formally verify models. The goal is to obtain first performance estimations of the system intended for design while minimizing the modeling effort. The contribution outlined in this paper is an additional module providing means for controlling the simulation in real time by performing step wise execution, saving and restoring simulation states as well as animating UML models of the system. Moreover the paper elaborates on the integration of these new features into the existing framework consisting of a simulation engine on the one hand and a graphical user interface on the other hand

Space-time-frequency methods for interference-limited communication systems

textTraditionally, noise in communication systems has been modeled as an additive, white Gaussian noise process with independent, identically distributed samples. Although this model accurately reflects thermal noise present in communication system electronics, it fails to capture the statistics of interference and other sources of noise, e.g. in unlicensed communication bands. Modern communication system designers must take into account interference and non-Gaussian noise to maximize efficiencies and capacities of current and future communication networks. In this work, I develop new multi-dimensional signal processing methods to improve performance of communication systems in three applications areas: (i) underwater acoustic, (ii) powerline, and (iii) multi-antenna cellular. In underwater acoustic communications, I address impairments caused by strong, time-varying and Doppler-spread reverberations (self-interference) using adaptive space-time signal processing methods. I apply these methods to array receivers with a large number of elements. In powerline communications, I address impairments caused by non-Gaussian noise arising from devices sharing the powerline. I develop and apply a cyclic adaptive modulation and coding scheme and a factor-graph-based impulsive noise mitigation method to improve signal quality and boost link throughput and robustness. In cellular communications, I develop a low-latency, high-throughput space-time-frequency processing framework used for large scale (up to 128 antenna) MIMO. This framework is used in the world's first 100-antenna MIMO system and processes up to 492 Gbps raw baseband samples in the uplink and downlink directions. My methods prove that multi-dimensional processing methods can be applied to increase communication system performance without sacrificing real-time requirements.Electrical and Computer Engineerin

Versatile event correlation with algebraic effects

We present the first language design to uniformly express variants of n -way joins over asynchronous event streams from different domains, e.g., stream-relational algebra, event processing, reactive and concurrent programming. We model asynchronous reactive programs and joins in direct style, on top of algebraic effects and handlers. Effect handlers act as modular interpreters of event notifications, enabling fine-grained control abstractions and customizable event matching. Join variants can be considered as cartesian product computations with ”degenerate” control flow, such that unnecessary tuples are not materialized a priori. Based on this computational interpretation, we decompose joins into a generic, naive enumeration procedure of the cartesian product, plus variant-specific extensions, represented in terms of user-supplied effect handlers. Our microbenchmarks validate that this extensible design avoids needless materialization. Alongside a formal semantics for joining and prototypes in Koka and multicore OCaml, we contribute a systematic comparison of the covered domains and features. ERC, Advanced Grant No. 321217 ERC, Consolidator Grant No. 617805 DFG, SFB 1053 DFG, SA 2918/2-

Model-based specification and design of large-scale embedded signal processing systems

In the digital part of large-scale phase array radio telescopes, the dominant streaming signal processing part is configured at run-time through a reactive and decentralized control and monitoring part. Interfacing and synchronizing these two parts without altering the behavior and performance of the dominant signal processing part is an issue when they are first considered in isolation. To address this issue before going to implementation, we propose to raise the level of abstraction, by expressing system-level specifications (in terms of application, architecture, and mapping) based on models. In the application model, the model of the control part and the model of the signal processing part are synchronized based on a notion of time that is known only to the control part. In the architecture model, the control model has a tree-like structure, whose leave nodes are interfaced with the computational nodes in the signal processing part. The mapping is based on iterative and interactive transformations that lead to an implementation-level specification, from where we consider that different implementation tools can take over to implement different parts of the system.UBL - phd migration 201