High-speed radix-10 multiplication using partial shifter adder tree-based convertor

A radix-10 multiplication is the foremost frequent operations employed by several monetary business and user-oriented applications, decimal multiplier using in state of art digital systems are significantly good but can be upgraded with time delay and area optimization. This work is proposed a more area and time delay optimized new design of overloaded decimal digit set (ODDS) architecture-based radix-10 multiplier for signed numbers. Binary coded decimal (BCD) to binary followed by binary multiplication and finally binary to BCD conversion are 3 major modules employed in radix-10 multiplication. This paperwork presents a replacement technique for binary coded decimal (BCD) to binary and vice-versa convertors in radix-10 multiplication. A novel addition tree structure called as partial shifter adder (PSA) tree-based approach has been developed for BCD to binary conversion, and it is used to add partially generated products. To meet our major concern i.e. speed, we need particular high-speed multiplication, hence the proposed PSA based radix-10 multiplier is using vertical cross binary multiplication and concurrent shifter-based addition method. The design has been tested on 45nm technology-based Zynq-7 field programmable gate array (FPGA) devices with a 6-input lookup table (LUTs). A combinational implementation maps quite well into the slice structure of the Xilinx Zynq-7 families field programmable gate array. The synthesis results for a Zynq-7 device indicate that our design outperforms in terms of the area and time delay

RADIX-10 PARALLEL DECIMAL MULTIPLIER

This paper introduces novel architecture for Radix-10 decimal multiplier. The new generation of highperformance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multiplier. The parallel generation of partial products is performed using signed-digit radix-10 recoding of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a new algorithm decimal multioperand carry-save addition that uses a unconventional decimal-coded number systems. We further detail these techniques and it significantly improves the area and latency of the previous design, which include: optimized digit recoders, decimal carry-save adders (CSA’s) combining different decimal-coded operands, and carry free adders implemented by special designed bit counters

HIGH-SPEED CO-PROCESSORS BASED ON REDUNDANT NUMBER SYSTEMS

There is a growing demand for high-speed arithmetic co-processors for use in applications with computationally intensive tasks. For instance, Fast Fourier Transform (FFT) co-processors are used in real-time multimedia services and financial applications use decimal co-processors to perform large amounts of decimal computations. Using redundant number systems to eliminate word-wide carry propagation within interim operations is a well-known technique to increase the speed of arithmetic hardware units. Redundant number systems are mostly useful in applications where many consecutive arithmetic operations are performed prior to the final result, making it advantageous for arithmetic co-processors. This thesis discusses the implementation of two popular arithmetic co-processors based on redundant number systems: namely, the binary FFT co-processor and the decimal arithmetic co-processor. FFT co-processors consist of several consecutive multipliers and adders over complex numbers. FFT architectures are implemented based on fixed-point and floating-point arithmetic. The main advantage of floating-point over fixed-point arithmetic is the wide dynamic range it introduces. Moreover, it avoids numerical issues such as scaling and overflow/underflow concerns at the expense of higher cost. Furthermore, floating-point implementation allows for an FFT co-processor to collaborate with general purpose processors. This offloads computationally intensive tasks from the primary processor. The first part of this thesis, which is devoted to FFT co-processors, proposes a new FFT architecture that uses a new Binary-Signed Digit (BSD) carry-limited adder, a new floating-point BSD multiplier and a new floating-point BSD three-operand adder. Finally, a new unit labeled as Fused-Dot-Product-Add (FDPA) is designed to compute AB+CD+E over floating-point BSD operands. The second part of the thesis discusses decimal arithmetic operations implemented in hardware using redundant number systems. These operations are popularly used in decimal floating-point co-processors. A new signed-digit decimal adder is proposed along with a sequential decimal multiplier that uses redundant number systems to increase the operational frequency of the multiplier. New redundant decimal division and square-root units are also proposed. The architectures proposed in this thesis were all implemented using Hardware-Description-Language (Verilog) and synthesized using Synopsys Design Compiler. The evaluation results prove the speed improvement of the new arithmetic units over previous pertinent works. Consequently, the FFT and decimal co-processors designed in this thesis work with at least 10% higher speed than that of previous works. These architectures are meant to fulfill the demand for the high-speed co-processors required in various applications such as multimedia services and financial computations

BCD REPETITIVE STRATEGY TO DECREASE THE LATENCY

We present the formula and architecture of the BCD parallel multiplier that exploits some qualities of two different redundant BCD codes to hurry up its computation: the redundant BCD excess-3 code (XS-3), and also the overloaded BCD representation (ODDS). Additionally, new techniques are designed to reduce considerably the latency and section of previous representative high end implementations. Partial goods are generated in parallel utilizing a signed-digit radix-10 recoding from the BCD multiplier using the digit set [-5, 5], and some positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) created in XS-3. This encoding has lots of advantages. First, it's a self-complementing code, to ensure that an adverse multiplicand multiple could be acquired just by inverting the items of the related positive one. Finally, the partial products could be recoded towards the ODDS representation just by adding a continuing factor in to the partial product reduction tree. Because the ODDS utilize a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, for example binary carry-save adders and compressor trees, could be adapted efficiently to do decimal operations. We reveal that the suggested decimal multiplier comes with an area improvement roughly within the range 20-35 % for similar target delays with regards to the fastest implementation

REDUCING LATENCY AND RECEIVING HIGH-RECITAL IN ANALOGOUS MULTIPLIERS

Partial goods are generated in parallel utilizing a signed-digit radix-10 recoding from the BCD multiplier using the digit set [-5, 5], and some positive multiplicand multiples (0X, 1X, 2X, 3X, 4X, 5X) created in XS-3. This encoding has lots of advantages. We present the formula and architecture of the BCD parallel multiplier that exploits some qualities of two different redundant BCD codes to hurry up its computation: the redundant BCD excess-3 code (XS-3), and also the overloaded BCD representation (ODDS). Additionally, new techniques are designed to reduce considerably the latency and section of previous representative high end implementations. First, it's a self-complementing code, to ensure that an adverse multiplicand multiple could be acquired just by inverting the items of the related positive one. Also, the accessible redundancy enables a easy and quick generation of multiplicand multiples inside a carry-free way. Finally, the partial products could be recoded towards the ODDS representation just by adding a continuing factor in to the partial product reduction tree. To exhibit the benefits of our architecture, we've synthesized a RTL model for 16 x 16-digit and 34 x 34-digit multiplications and performed a comparative survey from the previous most representative designs. Because the ODDS utilize a similar 4-bit binary encoding as non-redundant BCD, conventional binary VLSI circuit techniques, for example binary carry-save adders and compressor trees, could be adapted efficiently to do decimal operations

DESIGN THE PARALLEL MULTIPLIER BY USING REDUNDANT BCD CODES

We current the data and construction of a BCD complimentary multiplier that exploits some properties of two extraordinary de troop BCD codes to jog its calculation: the unnecessary BCD excess-3 code (XS-3), and the overloaded BCD eradiation (ODDS). In boost, new techniques perform to bring far the latency and area of proceeding reread active high-speed implementations. Partial commodities rise in correlate accepting a signed-finger radix-10 recoding of the BCD multiplier with the pointer set [-5, 5], and a set of reasonable multiplicand legions (0X, 1X, 2X, 3X, 4X, 5X) classify in XS-3. This encoding has sundry advantages. First, it is a self-complementing code, to prevent an unfavourable multiplicand multiplex perhaps obtained by just inverting the bits of the interrelated practical one. Also, the free attrition allows a fast and straightforward period of multiplicand legions in a bear free way. Finally, the one-sided produces perhaps rearrange to the ODDS recurrent action by just adding a constant circumstance into the one-sided commodity contraction tree. Since the ODDS uses a similar 4-bit doubled encoding as non-superfluous BCD, ordinary double VLSI lap techniques, such as paired publish-save adder and compressor trees, perhaps becoming carefully to represent ordinal operations. To show the advantages of our construction, we have synthesized an RTL model for 16-pointer and 34-pointer multiplications and executed a provisional evaluate of the past most generative designs

A HIGH PERFORMANCE RADIX10 MULTIPLICATION ARCHITECTURE BASED ON REDUNDANT BCD CODES

The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. It has been revived in recent years due to the large amount of data in commercial applications. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multi operand SD addition algorithm to reduce the partial product array. We consider the problem of multi operand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spread sheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool. In this project Xilinx-ISE tool is used for simulation, logical verification, and further synthesizing

IMPLEMENTATION OF POWER AND DELAY VARIANT OF A RADIX-10 COMBINATIONAL MULTIPLIER USING MIXED BINARY AND BCD CODE

The decimal multiplication is one of the most important decimal arithmetic operations which have a growing demand in the area of commercial, financial, and scientific computing. It has been revived in recent years due to the large amount of data in commercial applications. In this paper, we propose a parallel decimal multiplication algorithm with three components, which are a partial product generation, a partial product reduction, and a final digit-set conversion. First, a redundant number system is applied to recode not only the multiplier, but also multiples of the multiplicand in signed-digit (SD) numbers. Furthermore, we present a multi operand SD addition algorithm to reduce the partial product array.We consider the problem of multi operand parallel decimal addition with an approach that uses binary arithmetic, suggested by the adoption of binary-coded decimal (BCD) numbers. This involves corrections in order to obtain the BCD result or a binary-to-decimal (BD) conversion. The BD conversion moreover allows an easy alignment of the sums of adjacent columns. We treat the design of BCD digit adders using fast carry-free adders and the conversion problem through a known parallel scheme using elementary conversion cells. Spread sheets have been developed for adding several BCD digits and for simulating the BD conversion as a design tool. In this project Xilinx-ISE tool is used for simulation, logical verification, and further synthesizing

Analysis and implementation of decimal arithmetic hardware in nanometer CMOS technology

Scope and Method of Study: In today's society, decimal arithmetic is growing considerably in importance given its relevance in financial and commercial applications. Decimal calculations on binary hardware significantly impact performance mainly because most systems utilize software to emulate decimal calculations. The introduction of dedicated decimal hardware on the other hand promises the ability to improve performance by two or three orders of magnitude. The founding blocks of binary arithmetic are studied and applied to the development of decimal arithmetic hardware. New findings are contrasted with existent implementations and validated through extensive simulation.Findings and Conclusions: New architectures and a significant study of decimal arithmetic was developed and implemented. The architectures proposed include an IEEE-754 current revision draft compliant floating-point comparator, a study on decimal division, partial product reduction schemes using decimal compressor trees and a final implementation of a decimal multiplier using advanced techniques for partial product generation. The results of each hardware implementation in nanometer technologies are weighed against existent propositions and show improvements upon area, delay, and power