Development of a Nanosatellite Software Defined Radio Communications System

Communications systems designed with application-specific integrated circuit (ASIC) technology suffer from one very significant disadvantage - the integrated circuits do not possess the ability of programmability. However, Software Defined Radio’s (SDR’s) integrated with Field Programmable Gate Arrays (FPGA) provide an opportunity to update the communication system on nanosatellites (which are physically difficult to access) due to their capability of performing signal processing in software. SDR signal processing is performed in software on reprogrammable elements such as FPGA’s. Applying this technique to nanosatellite communications systems will optimize the operations of the hardware, and increase the flexibility of the system. In this research a transceiver algorithm for a nanosatellite software defined radio communications is designed. The developed design is capable of modulation of data to transmit information and demodulation of data to receive information. The transceiver algorithm also works at different baud rates. The design implementation was successfully tested with FPGA-based hardware to demonstrate feasibility of the transceiver design with a hardware platform suitable for SDR implementation

Definition of a FPGA-based SoC architecture for PRBS transmission in optical spectroscopy

Optical spectroscopy is a well-known tool typically employed for characterizing the properties of materials by analyzing their iteration with light. One of the most spread techniques is the dual comb spectroscopy, since it accomplishes ultra-high resolution, and high sensitivity measurements with a relatively simple platform including a single, relatively narrowband photodetector. The employed optical dual comb can be implemented through electro-optical (EO) modulation driven by pseudo-ransom binary sequences (PRBS) at high data rates, commonly in the range of tens of Gbps. For that purpose, the runtime generation and transmission of adaptive PRBS is still an open challenge, often involving expensive and not flexible high-speed digital systems, with a few commercially available solutions that sometimes do not match the application requirements efficiently. In this context, this work describes the definition and implementation of a System-on-Chip (SoC) architecture, based on a FPGA device, capable of generating and transmitting two PRBS for a dual comb, at a data rate up to 5 Gbps. The architecture can be configured and its operation modified in run time, thanks to the general-purpose processor involved, in charge of managing an Ethernet link to receive new PRBS to be transmitted or set up certain parameters. The proposed design has been validated experimentally on a dual comb spectroscopy measurement, where the absorption of a hydrogen cyanide (HCN) gas cell has been successfully characterized.Agencia Estatal de InvestigaciónMinisterio de Ciencia e Innovació

Controlling and Processing Core for Wireless Implantable Telemetry System

Wireless implantable telemetry systems are suitable choices for monitoring various physiological parameters such as blood pressure and volume. These systems typically compose of an internal device implanted into a living body captures the physiological data and sends them to an external base station located outside of the body for further processing. The internal device usually consists of a sensor interface to convert the collected data to electrical signals; a digital core to digitize the analog signals, process them and prepare them for transmission; an RF front-end to transmit the data outside the body and to receive the required commands from the end station; and a wireless power supply. The digital core plays an important role in these systems since the data must be digitized and processed before transmitting to the end station for further processing. In this thesis, we presented an FPGA-based prototype for controlling and processing core of a miniature implantable telemetry system that is used to monitoring physiological parameters of laboratory small animals. The presented module samples and digitizes the collected data using an analog to digital converter, stores the collected data, generates the controlling output commands, processing the received data, and controls the power consumption of the system. The circuit is prototyped and experimentally verified using an FPGA development platform, then synthesized and simulated in 130 nm CMOS IC technology using standard digital cells. The overall core design occupies 1.6 mm × 1.6 mm CMOS area, and consumes 14.5 mW (IC) or 208 mW (FPGA) total power

Design and implementation of an SDR-based multi-frequency ground-based SAR system

Synthetic Aperture Radar (SAR) has proven a valuable tool in the monitoring of the Earth, either at a global or local scales. SAR is a coherent radar system able to image extended areas with high resolution, and finds applications in many areas such as forestry, agriculture, mining, structure inspection or security operations. Although space-borne SAR systems can image extended areas, their main limitation is the long revisit times, which are not suitable for applications where the target experiments rapid changes, in the scale of minutes to few days. GBSAR systems have proven useful to fill this revisit time gap by imaging relatively small areas continuously, with extensions usually smaller than a few square kilometers. Ground Based SAR (GBSAR) systems have been used extensively for the monitoring of slope instability, and are a common tool in the mining sector. The development of the GBSAR is relatively recent, and various developments have taken place since the 2000s, transitioning from the usage of Vector Network Analyzers (VNAs) to custom radar cores tailored for this application. This transition is accompanied by a reduction in cost, but at the same time is accompanied by a loss of operational flexibility. Specifically, most GBSAR sensors now operate at a single frequency, losing the value of the multi-band operation that VNAs provided. This work is motivated by the idea that it is worth to use the value of multi-frequency GBSAR measurements, while maintaining a limited system cost. In order to implement a GBSAR with these characteristics, it is realized that Software Defined Radio (SDR) devices are a good option for fast and flexible implementation of broadband transceivers. This thesis details the design and implementation process of an SDR-based Frequency Modulated Continuous Wave (FMCW) GBSAR system from the ground up, presenting the main issues related with the usage of the most common SDR analog architecture, the Zero-IF transceiver. The main problem is determined to be the behavior of spurs related to IQ imbalances of the analog transceiver with the FMCW demodulation process. Two effective techniques to overcome these issues, the Super Spatial Variant Apodization (SSVA) and the Short Time Fourier Transform (STFT) signal reconstruction techniques, are implemented and tested. The thesis also deals with the digital implementation of the signal generator and digital receiver, which are implemented on top of an RF Network-on-Chip (RFNoC) architecture in the SDR Field Programmable Gate Array (FPGA). Another important aspect of this work is the development of an radiofrequency front-end that extends the capabilities of the SDR, implementing filtering, amplification, leakage mitigation and up-conversion to X-band. Finally, a set of test campaigns is described, in which the operation of the system is verified and the value of multi-frequency GBSAR observations is shown.El radar d'obertura sintètica (SAR) ha demostrat ser una eina valuosa en el monitoratge de la Terra, sigui a escala global o local. El SAR és un sistema de radar coherent capaç d’obtenir imatges de zones extenses amb alta resolució i té aplicacions en moltes àrees com la silvicultura, l’agricultura, la mineria, la inspecció d’estructures o les operacions de seguretat. Tot i que els sistemes SAR embarcats en plataformes orbitals poden obtenir imatges d'àrees extenses, la seva principal limitació és el temps de revisita, que no són adequats per a aplicacions on l'objectiu experimenta canvis ràpids, en una escala de minuts a pocs dies. Els sistemes GBSAR han demostrat ser útils per omplir aquesta bretxa de temps, obtenint imatges d'àrees relativament petites de manera contínua, amb extensions generalment inferiors a uns pocs quilòmetres quadrats. Els sistemes SAR terrestres (GBSAR) s’han utilitzat àmpliament per al control de la inestabilitat de talussos i esllavissades i són una eina comuna al sector miner. El desenvolupament del GBSAR és relativament recent i s’han produït diversos desenvolupaments des de la dècada de 2000, passant de l’ús d’analitzadors de xarxes vectorials (VNA) a nuclis de radar personalitzats i adaptats a aquesta aplicació. Aquesta transició s’acompanya d’una reducció del cost, però al mateix temps d’una pèrdua de flexibilitat operativa. Concretament, la majoria dels sensors GBSAR funcionen a una única freqüència, perdent el valor de l’operació en múltiples bandes que proporcionaven els VNA. Aquesta tesi està motivada per la idea de recuperar el valor de les mesures GBSAR multifreqüència, mantenint un cost del sistema limitat. Per tal d’implementar un GBSAR amb aquestes característiques, s’adona que els dispositius de ràdio definida per software (SDR) són una bona opció per a la implementació ràpida i flexible dels transceptors de banda ampla. Aquesta tesi detalla el procés de disseny i implementació d’un sistema GBSAR d’ona contínua modulada en freqüència (FMCW) basat en la tecnologia SDR, presentant els principals problemes relacionats amb l’ús de l’arquitectura analògica de SDR més comuna, el transceptor Zero-IF. Es determina que el problema principal és el comportament dels espuris relacionats amb el balanç de les cadenes de fase i quadratura del transceptor analògic amb el procés de desmodulació FMCW. S’implementen i comproven dues tècniques efectives per minimitzar aquests problemes basades en la reconstrucció de la senyal contaminada per espuris: la tècnica anomenada Super Spatial Variant Apodization (SSVA) i una tècnica basada en la transformada de Fourier amb finestra (STFT). La tesi també tracta la implementació digital del generador de senyal i del receptor digital, que s’implementen sobre una arquitectura RF Network-on-Chip (RFNoC). Un altre aspecte important d’aquesta tesi és el desenvolupament d’un front-end de radiofreqüència que amplia les capacitats de la SDR, implementant filtratge, amplificació, millora de l'aïllament entre transmissió i recepció i conversió a banda X. Finalment, es descriu un conjunt de campanyes de prova en què es verifica el funcionament del sistema i es mostra el valor de les observacions GBSAR multifreqüència

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

The field programmable gate array (FPGA) devices are ideal solutions for high-speed processing applications, given their flexibility, parallel processing capability, and power efficiency. In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices. FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (MIMO) channel characterizers are the main considered applications that can benefit from the high processing rate, power efficiency and flexibility of FPGAs. Furthermore, the implementations of encryption/decryption algorithms by employing the Xilinx Zynq Ultrascale+MPSoC ZCU102 FPGA platform are discussed, and then we introduce our high-speed and lightweight implementation of the well-known AES-128 algorithm, developed on the same FPGA platform, and comparing it with similar solutions already published in the literature. The comparison results indicate that our AES-128 implementation enables efficient hardware usage for a given data-rate (up to 28.16 Gbit/s), resulting in higher efficiency (8.64 Mbps/slice) than other considered solutions. Finally, the applications of the ZCU102 platform for high-speed processing are explored, such as image and signal processing, visual recognition, and hardware resource management

Design and Implementation of a Fully Flexible Cognitive Radio Modem

Software-defined radio (SDR)-based cognitive communication radio systems are very popular at present, and there have been many investigations on this topic. This paper proposes a new type of cognitive radio transceiver (TRX) that can detect, recognize, and analyze input signals in real-time with minimal data loss. New hardware is designed and manufactured that combines a transmitter and a receiver in a dedicated integrated circuit. For data processing, a field-programmable gate array (FPGA) is used. For each integrated hardware block, appropriate software modules are developed to construct a complex adaptive radiocommunication system as a radio modem that can be configured as a transceiver or repeater. The source coder, channel coder, modulator, spectrum monitoring module, spectrum analyzer, channelizer, symbol rate detector, modulator, modulation type recognition module, demodulator, channel decoder and source decoder are all developed as software modules

Portable Waveform Development for Software Defined Radios

This work focuses on the question: "How can we build waveforms that can be moved from one platform to another?\u27\u27 Therefore an approach based on the Model Driven Architecture was evaluated. Furthermore, a proof of concept is given with the port of a TETRA waveform from a USRP platform to an SFF SDR platform

Automatic transmit power control for power efficient communications in UAS

Nowadays, unmanned aerial vehicles (UAV) have become one of the most popular tools that can be used in commercial, scientific, agricultural and military applications. As drones become faster, smaller and cheaper, with the ability to add payloads, the usage of the drone can be versatile. In most of the cases, unmanned aerials systems (UAS) are equipped with a wireless communication system to establish a link with the ground control station to transfer the control commands, video stream, and payload data. However, with the limited onboard calculation resources in the UAS, and the growing size and volume of the payload data, computational complex signal processing such as deep learning cannot be easily done on the drone. Hence, in many drone applications, the UAS is just a tool for capturing and storing data, and then the data is post-processed off-line in a more powerful computing device. The other solution is to stream payload data to the ground control station (GCS) and let the powerful computer on the ground station to handle these data in real-time. With the development of communication techniques such as orthogonal frequency-division multiplexing (OFDM) and multiple-input multiple-output (MIMO) transmissions, it is possible to increase the spectral efficiency over large bandwidths and consequently achieve high transmission rates. However, the drone and the communication system are usually being designed separately, which means that regardless of the situation of the drone, the communication system is working independently to provide the data link. Consequently, by taking into account the position of the drone, the communication system has some room to optimize the link budget efficiency. In this master thesis, a power-efficient wireless communication downlink for UAS has been designed. It is achieved by developing an automatic transmit power control system and a custom OFDM communication system. The work has been divided into three parts: research of the drone communication system, an optimized communication system design and finally, FPGA implementation. In the first part, an overview on commercial drone communication schemes is presented and discussed. The advantages and disadvantages shown are the source of inspiration for improvement. With these ideas, an optimized scheme is presented. In the second part, an automatic transmit power control system for UAV wireless communication and a power-efficient OFDM downlink scheme are proposed. The automatic transmit power control system can estimate the required power level by the relative position between the drone and the GCS and then inform the system to adjust the power amplifier (PA) gain and power supply settings. To obtain high power efficiency for different output power levels, a searching strategy has been applied to the PA testbed to find out the best voltage supply and gain configurations. Besides, the OFDM signal generation developed in Python can encode data bytes to the baseband signal for testing purpose. Digital predistortion (DPD) linearization has been included in the transmitter’s design to guarantee the signal linearity. In the third part, two core algorithms: IFFT and LUT-based DPD, have been implemented in the FPGA platform to meet the real-time and high-speed I/O requirements. By using the high-level synthesis design process provided by Xilinx Corp, the algorithms are implemented as reusable IP blocks. The conclusion of the project is given in the end, including the summary of the proposed drone communication system and envisioning possible future lines of research