Experimental verification of the usefulness of the nth power law MOSFET model under hot carrier wearout

4 pagesInternational audienceIn this paper the usefulness of the nth power law MOSFET model under Hot Carrier Injection (HCI) wearout has been experimentally demonstrated. In order to do that, three types of nFET transistors have been analyzed under different HCI conditions and the nth power law MOSFET model has been extracted for each sample. The results show that the model can reproduce the MOSFET behavior under HCI wearout mechanism. Therefore, the impact of HCI on circuits can be analyzed by using the nth power law MOSFET model

CMOS analog-digital circuit components for low power applications

Dissertação de mestrado em Micro and NanoelectronicsThis dissertation presents a study in the area of mixed analog/digital CMOS power extraction circuits for energy harvester. The main contribution of this work is the realization of low power consumption and high efficient circuit components employable in a management circuit for piezoelectricbased energy harvester. This thesis focuses on the development of current references and operational amplifiers addressing low power demands. A brief literature review is conducted on the components necessary for the power extraction circuit, including introduction to CMOS technology design and research of known low power circuits. It is presented with multiple implementations for voltage and current references, as well for operational amplifier designs. A self-biased current reference, capable of driving the remaining harvesting circuit, is designed and verified. A novel operational amplifier is proposed by the use of a minimum current selector circuit topology. It is a three-stage amplifier with an AB class output stage, comprised by a translinear circuit. The circuit is designed, taking into consideration noise reduction. The circuit components are designed based on the 0.35mm CMOS technology. A physical layout is developed for fabrication purposes. This technology was chosen with consideration of robustness, costliness and performance. The current reference is capable of outputting a stable 12nA current, which may remain stable in a broad range of power supply voltages with a minimum voltage of 1.6V. The operational amplifier operates correctly at voltages as low as 1.5V. The amplifier power consumption is extremely low, around 8mW, with an optimal quiescent current and minimum current preservation in the output stage.A principal contribuição desta dissertação é a implementação de circuitos integrados de muito baixo consumo e alta eficiência, prontos a ser implementados num circuito de extração de energia com base num elemento piezoelétrico. Esta tese foca-se no desenvolvimento de um circuito de referência de corrente e um amplificador operacional com baixa exigência de consumo. Uma revisão da literatura é realizada, incluindo introdução à tecnologia Complementary Metal-Oxide-Semiconductor (CMOS), e implementação de conhecidos circuitos de baixo consumo. Várias implementações de referência de tensão e corrente são consideradas, e amplificadores operacionais também. Uma referência de corrente auto polarizada com extremo baixo consumo é desenvolvida e verificada. Um amplificador operacional original é proposto com uma topologia de seleção de corrente mínima. Este circuito é constituído por três estágios, com um estágio de saída de classe AB, e um circuito translinear. O circuito tem em consideração redução de ruído na sua implementação. Os circuitos são desenvolvidos com base na tecnologia 0.35mm CMOS. Uma layout foi também desenhada com o propósito de fabricação. A tecnologia foi escolhida tendo em conta o seu custo versus desempenho. A referência de corrente produz uma corrente de 12nA, permanecendo estável para tensões de alimentação de variáveis, com uma tensão mínima de 1.6V. O circuito mostra um coeficiente de temperatura satisfatório. O amplificador operacional funciona com tensão de alimentação mínima de 1.5V, com um consumo baixo de 8mW, com uma corrente mínima mantida no estágio de saída

Contribución al estudio de las interferencias electromagnéticas conducidas en circuitos integrados

This thesis is focused on the conducted electromagnetic Interference generated at Integrated Circuit (IC) Level. Recently, several electrical models have been proposed in order to describe EMI at IC level, but they have several limitations. The first drawback is that these electrical models do not take into account the wear-out mechanisms on the EMI behaviour. The wear-out mechanisms are due to the dielectric degradation when an electric stress is applied to the oxide gate. Due to this degradation, the MOSFET characteristics are shifted. Therefore, the evaluation of wear-out mechanisms allow the designers, during the IC design, to predict the circuit behaviour along its lifetime. However, the impact of these wear-out mechanisms on the conducted EMI drift at IC level has not been deeply investigated. Hence, one of the aims of this thesis will be focused on the impact of wear-out mechanisms in signal integrity and conducted EMI at IC level. Moreover, current integrated circuits have a high operation frequency. Thus, the electromagnetic noise induced on those devices presents a higher harmonic content. For this reason, the electronics industry requires electrical models to predict high frequency conducted emissions. In this sense, the other aim of this thesis will be focused on expanding the current EMI models beyond 1 GHz. The IC behaviour may be affected by temperature, as well as conducted emission levels. Therefore, the proposed electrical model will take into account the impact of temperature. The experimental results have been obtained with three integrated circuits, two of them are specific test chip designed by Freescale Semiconductor, Inc., and the third IC is a commercial circuit of Maxim Integrated Circuits. This document is structured in four chapters. Chapter 1 describes the main wear-out mechanisms and the electromagnetic compatibility at IC level. The different EMI produced at IC are explained. Also, it describes aging methods to characterize the impact of wear-out mechanisms on MOS devices. Furthermore, the EMI characterization methods are explained and different EMC electrical models are described. To confirm the accuracy of the EMC models, the ¿Feature Selective Validation¿ (FSV) technique has been used. On this chapter, the FSV method and its application on computational electromagnetism is detailed. The chapter ends with the state of the art on wear-out mechanisms and EMI at IC level. Chapter 2 analyzes the IC reliability. The IC aging of the MOSFET I-V curve characteristics is studied, for further EMI characterization of the impact of wear-out mechanisms. The experimental results are presented at the end of Chapter 2. Chapter 3 presents an electrical model to characterize the conducted emissions of an IC up to 3 GHz. This electrical model considers the impact of temperature. The proposed model is validated with experimental results and verified with the FSV method. Chapter 4 summarizes the conclusions of the thesis and the main contributions. In addition, a list of the publications derived from this thesis is included. Finally, the chapter presents the lines for future research.Esta tesis se centra en el estudio de las interferencias electromagnéticas (“Electromagnetic Interferences” o EMI) conducidas generadas a nivel de circuito integrado (CI). En la actualidad, existen modelos eléctricos para describir las EMI conducidas a nivel de CI, pero presentan ciertas limitaciones. La primera de ellas es que estos modelos no tienen en cuenta el impacto de los mecanismos de degradación sobre las EMI. Los mecanismos de degradación aparecen por el deterioro del dieléctrico debido al estrés eléctrico aplicado en el óxido de puerta. Estos mecanismos producen la variación de las características eléctricas de los dispositivos MOS. El estudio de estos efectos permite predecir, durante la etapa inicial del diseño, su impacto durante el tiempo de vida de los CI. Sin embargo, hasta la fecha, no se han llevado a cabo estudios del efecto de los mecanismos de degradación en las EMI conducidas a nivel de CI. Por lo tanto, uno de los primeros objetivos de la tesis será caracterizar el impacto de los mecanismos de degradación en la integridad de la señal y en las EMI conducidas a nivel de CI. Asimismo, los CI tienen una frecuencia de funcionamiento cada vez mayor, de modo que el ruido electromagnético generado por estos dispositivos tiene un contenido harmónico de más alta frecuencia. Es por esto que conviene tener modelos eléctricos que permitan modelizar las EMI de alta frecuencia. El segundo objetivo de la tesis consiste en modelizar las EMI conducidas más allá de la frecuencia de 1 GHz ya que los modelos actuales son válidos hasta esta frecuencia. La temperatura de funcionamiento del CI puede afectar al comportamiento del mismo, así como a los niveles de las emisiones conducidas. Por lo tanto será de interés que el modelo propuesto tenga en cuenta el impacto de la temperatura, ya que los modelos actuales únicamente son válidos para una temperatura de funcionamiento. La validación experimental se ha llevado a cabo sobre tres circuitos integrados, dos de ellos diseñados específicamente para este estudio por la empresa Freescale Semiconductor, Inc. y el tercer CI es un circuito comercial de Maxim Integrated Circuits. Este documento se compone de cuatro capítulos. El capítulo 1 empieza con la descripción de los principales mecanismos de degradación y de la compatibilidad electromagnética a nivel de circuito integrado. Se detallan las diferentes interferencias electromagnéticas que pueden producirse a nivel de circuito integrado. Se procede con la descripción de los métodos acelerados de envejecimiento para caracterizar el impacto de los mecanismos de degradación en los dispositivos MOS. Se continúa con una explicación de los métodos para caracterizar las EMI y la presentación de diferentes modelos EMC para su modelización. Para la validación de los estos modelos EMC se hace uso del método “Feature Selective Validation” (FSV). En este capítulo se da explicación al método FSV y su aplicación en el electromagnetismo computacional. Para finalizar el capítulo, se describe el estado actual de la investigación en el campo de los mecanismos de degradación y de las EMI a nivel de CI. En el capítulo 2 se analiza la fiabilidad de los CI. Se estudia el impacto de los mecanismos de degradación en el comportamiento de los transistores, para posteriormente estudiar el impacto de estos mecanismos en las EMI. El capítulo 2 se complementa con los resultados experimentales obtenidos en el laboratorio. El capítulo 3 se centra en la caracterización y el modelado de las EMI en los circuitos integrados. Se propone un modelo eléctrico para caracterizar las interferencias electromagnéticas conducidas hasta los 3 GHz y el impacto de la temperatura en las emisiones conducidas. El modelo propuesto es comprobado con medidas experimentales y verificado con el método FSV. Por último, el capítulo 4 resume las conclusiones de la tesis y las principales contribuciones. Además, en este capítulo se presenta las líneas de investigación futuras. Esta tesis se ha desarrollado dentro de una de las líneas de investigación del Grupo de Electrónica Industrial de Terrassa (“Terrassa Industrial Electronics Group” - TIEG), dentro del marco del proyecto de investigación TEC2009-09994, TEC2010-18550 y AGAUR 2009 SGR 142

Simulation study of scaling design, performance characterization, statistical variability and reliability of decananometer MOSFETs

This thesis describes a comprehensive, simulation based scaling study – including device design, performance characterization, and the impact of statistical variability – on deca-nanometer bulk MOSFETs. After careful calibration of fabrication processes and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length, 1 nm EOT and stress engineering, the simulated devices closely match the performance of contemporary 45 nm CMOS technologies. Scaling to 25 nm, 18 nm and 13 nm gate length n and p devices follows generalized scaling rules, augmented by physically realistic constraints and the introduction of high-k/metal-gate stacks. The scaled devices attain the performance stipulated by the ITRS. Device a.c. performance is analyzed, at device and circuit level. Extrinsic parasitics become critical to nano-CMOS device performance. The thesis describes device capacitance components, analyzes the CMOS inverter, and obtains new insights into the inverter propagation delay in nano-CMOS. The projection of a.c. performance of scaled devices is obtained. The statistical variability of electrical characteristics, due to intrinsic parameter fluctuation sources, in contemporary and scaled decananometer MOSFETs is systematically investigated for the first time. The statistical variability sources: random discrete dopants, gate line edge roughness and poly-silicon granularity are simulated, in combination, in an ensemble of microscopically different devices. An increasing trend in the standard deviation of the threshold voltage as a function of scaling is observed. The introduction of high-k/metal gates improves electrostatic integrity and slows this trend. Statistical evaluations of variability in Ion and Ioff as a function of scaling are also performed. For the first time, the impact of strain on statistical variability is studied. Gate line edge roughness results in areas of local channel shortening, accompanied by locally increased strain, both effects increasing the local current. Variations are observed in both the drive current, and in the drive current enhancement normally expected from the application of strain. In addition, the effects of shallow trench isolation (STI) on MOSFET performance and on its statistical variability are investigated for the first time. The inverse-narrow-width effect of STI enhances the current density adjacent to it. This leads to a local enhancement of the influence of junction shapes adjacent to the STI. There is also a statistical impact on the threshold voltage due to random STI induced traps at the silicon/oxide interface

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Predicting power scalability in a reconfigurable platform

This thesis focuses on the evolution of digital hardware systems. A reconfigurable platform is proposed and analysed based on thin-body, fully-depleted silicon-on-insulator Schottky-barrier transistors with metal gates and silicide source/drain (TBFDSBSOI). These offer the potential for simplified processing that will allow them to reach ultimate nanoscale gate dimensions. Technology CAD was used to show that the threshold voltage in TBFDSBSOI devices will be controllable by gate potentials that scale down with the channel dimensions while remaining within appropriate gate reliability limits. SPICE simulations determined that the magnitude of the threshold shift predicted by TCAD software would be sufficient to control the logic configuration of a simple, regular array of these TBFDSBSOI transistors as well as to constrain its overall subthreshold power growth. Using these devices, a reconfigurable platform is proposed based on a regular 6-input, 6-output NOR LUT block in which the logic and configuration functions of the array are mapped onto separate gates of the double-gate device. A new analytic model of the relationship between power (P), area (A) and performance (T) has been developed based on a simple VLSI complexity metric of the form ATσ = constant. As σ defines the performance “return” gained as a result of an increase in area, it also represents a bound on the architectural options available in power-scalable digital systems. This analytic model was used to determine that simple computing functions mapped to the reconfigurable platform will exhibit continuous power-area-performance scaling behavior. A number of simple arithmetic circuits were mapped to the array and their delay and subthreshold leakage analysed over a representative range of supply and threshold voltages, thus determining a worse-case range for the device/circuit-level parameters of the model. Finally, an architectural simulation was built in VHDL-AMS. The frequency scaling described by σ, combined with the device/circuit-level parameters predicts the overall power and performance scaling of parallel architectures mapped to the array

Design of Variation-Tolerant Circuits for Nanometer CMOS Technology: Circuits and Architecture Co-Design

Aggressive scaling of CMOS technology in sub-90nm nodes has created huge challenges. Variations due to fundamental physical limits, such as random dopants fluctuation (RDF) and line edge roughness (LER) are increasing significantly with technology scaling. In addition, manufacturing tolerances in process technology are not scaling at the same pace as transistor's channel length due to process control limitations (e.g., sub-wavelength lithography). Therefore, within-die process variations worsen with successive technology generations. These variations have a strong impact on the maximum clock frequency and leakage power for any digital circuit, and can also result in functional yield losses in variation-sensitive digital circuits (such as SRAM). Moreover, in nanometer technologies, digital circuits show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost while achieving higher performance and density. It is therefore not surprising that the International Technology Roadmap for Semiconductors (ITRS) lists variability as one of the most challenging obstacles for IC design in nanometer regime. To facilitate variation-tolerant design, we study the impact of random variations on the delay variability of a logic gate and derive simple and scalable statistical models to evaluate delay variations in the presence of within-die variations. This work provides new design insight and highlights the importance of accounting for the effect of input slew on delay variations, especially at lower supply voltages. The derived models are simple, scalable, bias dependent and only require the knowledge of easily measurable parameters. This makes them useful in early design exploration, circuit/architecture optimization as well as technology prediction (especially in low-power and low-voltage operation). The derived models are verified using Monte Carlo SPICE simulations using industrial 90nm technology. Random variations in nanometer technologies are considered one of the largest design considerations. This is especially true for SRAM, due to the large variations in bitcell characteristics. Typically, SRAM bitcells have the smallest device sizes on a chip. Therefore, they show the largest sensitivity to different sources of variations. With the drastic increase in memory densities, lower supply voltages and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. In this research, we present a methodology for statistical simulation of SRAM read access yield, which is tightly related to SRAM performance and power consumption. The proposed flow accounts for the impact of bitcell read current variation, sense amplifier offset distribution, timing window variation and leakage variation on functional yield. The methodology overcomes the pessimism existing in conventional worst-case design techniques that are used in SRAM design. The proposed statistical yield estimation methodology allows early yield prediction in the design cycle, which can be used to trade off performance and power requirements for SRAM. The methodology is verified using measured silicon yield data from a 1Mb memory fabricated in an industrial 45nm technology. Embedded SRAM dominates modern SoCs and there is a strong demand for SRAM with lower power consumption while achieving high performance and high density. However, in the presence of large process variations, SRAMs are expected to consume larger power to ensure correct read operation and meet yield targets. We propose a new architecture that significantly reduces array switching power for SRAM. The proposed architecture combines built-in self-test (BIST) and digitally controlled delay elements to reduce the wordline pulse width for memories while ensuring correct read operation; hence, reducing switching power. A new statistical simulation flow was developed to evaluate the power savings for the proposed architecture. Monte Carlo simulations using a 1Mb SRAM macro from an industrial 45nm technology was used to examine the power reduction achieved by the system. The proposed architecture can reduce the array switching power significantly and shows large power saving - especially as the chip level memory density increases. For a 48Mb memory density, a 27% reduction in array switching power can be achieved for a read access yield target of 95%. In addition, the proposed system can provide larger power saving as process variations increase, which makes it a very attractive solution for 45nm and below technologies. In addition to its impact on bitcell read current, the increase of local variations in nanometer technologies strongly affect SRAM cell stability. In this research, we propose a novel single supply voltage read assist technique to improve SRAM static noise margin (SNM). The proposed technique allows precharging different parts of the bitlines to VDD and GND and uses charge sharing to precisely control the bitline voltage, which improves the bitcell stability. In addition to improving SNM, the proposed technique also reduces memory access time. Moreover, it only requires one supply voltage, hence, eliminates the need of large area voltage shifters. The proposed technique has been implemented in the design of a 512kb memory fabricated in 45nm technology. Results show improvements in SNM and read operation window which confirms the effectiveness and robustness of this technique