Graphical models for mediation analysis

Mediation analysis seeks to infer how much of the effect of an exposure on an outcome can be attributed to specific pathways via intermediate variables or mediators. This requires identification of so-called path-specific effects. These express how a change in exposure affects those intermediate variables (along certain pathways), and how the resulting changes in those variables in turn affect the outcome (along subsequent pathways). However, unlike identification of total effects, adjustment for confounding is insufficient for identification of path-specific effects because their magnitude is also determined by the extent to which individuals who experience large exposure effects on the mediator, tend to experience relatively small or large mediator effects on the outcome. This chapter therefore provides an accessible review of identification strategies under general nonparametric structural equation models (with possibly unmeasured variables), which rule out certain such dependencies. In particular, it is shown which path-specific effects can be identified under such models, and how this can be done

MERLiN: Mixture Effect Recovery in Linear Networks

Causal inference concerns the identification of cause-effect relationships between variables, e.g. establishing whether a stimulus affects activity in a certain brain region. The observed variables themselves often do not constitute meaningful causal variables, however, and linear combinations need to be considered. In electroencephalographic studies, for example, one is not interested in establishing cause-effect relationships between electrode signals (the observed variables), but rather between cortical signals (the causal variables) which can be recovered as linear combinations of electrode signals. We introduce MERLiN (Mixture Effect Recovery in Linear Networks), a family of causal inference algorithms that implement a novel means of constructing causal variables from non-causal variables. We demonstrate through application to EEG data how the basic MERLiN algorithm can be extended for application to different (neuroimaging) data modalities. Given an observed linear mixture, the algorithms can recover a causal variable that is a linear effect of another given variable. That is, MERLiN allows us to recover a cortical signal that is affected by activity in a certain brain region, while not being a direct effect of the stimulus. The Python/Matlab implementation for all presented algorithms is available on https://github.com/sweichwald/MERLi

New techniques for functional testing of microprocessor based systems

Electronic devices may be affected by failures, for example due to physical defects. These defects may be introduced during the manufacturing process, as well as during the normal operating life of the device due to aging. How to detect all these defects is not a trivial task, especially in complex systems such as processor cores. Nevertheless, safety-critical applications do not tolerate failures, this is the reason why testing such devices is needed so to guarantee a correct behavior at any time. Moreover, testing is a key parameter for assessing the quality of a manufactured product. Consolidated testing techniques are based on special Design for Testability (DfT) features added in the original design to facilitate test effectiveness. Design, integration, and usage of the available DfT for testing purposes are fully supported by commercial EDA tools, hence approaches based on DfT are the standard solutions adopted by silicon vendors for testing their devices. Tests exploiting the available DfT such as scan-chains manipulate the internal state of the system, differently to the normal functional mode, passing through unreachable configurations. Alternative solutions that do not violate such functional mode are defined as functional tests. In microprocessor based systems, functional testing techniques include software-based self-test (SBST), i.e., a piece of software (referred to as test program) which is uploaded in the system available memory and executed, with the purpose of exciting a specific part of the system and observing the effects of possible defects affecting it. SBST has been widely-studies by the research community for years, but its adoption by the industry is quite recent. My research activities have been mainly focused on the industrial perspective of SBST. The problem of providing an effective development flow and guidelines for integrating SBST in the available operating systems have been tackled and results have been provided on microprocessor based systems for the automotive domain. Remarkably, new algorithms have been also introduced with respect to state-of-the-art approaches, which can be systematically implemented to enrich SBST suites of test programs for modern microprocessor based systems. The proposed development flow and algorithms are being currently employed in real electronic control units for automotive products. Moreover, a special hardware infrastructure purposely embedded in modern devices for interconnecting the numerous on-board instruments has been interest of my research as well. This solution is known as reconfigurable scan networks (RSNs) and its practical adoption is growing fast as new standards have been created. Test and diagnosis methodologies have been proposed targeting specific RSN features, aimed at checking whether the reconfigurability of such networks has not been corrupted by defects and, in this case, at identifying the defective elements of the network. The contribution of my work in this field has also been included in the first suite of public-domain benchmark networks

Understanding Covid-19 Mobility Through Human Capital: A Unified Causal Framework

This paper seeks to identify the causal impact of educational human capital on social distancing behavior at workplace in Turkey using district-level data for the period of April 2020 - February 2021. We adopt a unified causal framework, predicated on domain knowledge, theory-justified constraints anda data-driven causal structure discovery using causal graphs. We answer our causal query by employing machine learning prediction algorithms; instrumental variables in the presence of latent confounding and Heckman's model in the presence of selection bias. Results show that educated regions are able to distance-work and educational human capital is a key factor in reducing workplace mobility, possibly through its impact on employment. This pattern leads to higher workplace mobility for less educated regions and translates into higher Covid-19 infection rates. The future of the pandemic lies in less educated segments of developing countries and calls for public health action to decrease its unequal and pervasive impact.WOS:0009378408000012-s2.0-8514846576136844967Science Citation Index Expanded-Social Sciences Citation IndexarticleUluslararası işbirliği ile yapılmayan - HAYIRMart2023YÖK - 2022-2

COMPATIBILITY TESTING FOR COMPONENT-BASED SYSTEMS

Many component-based systems are deployed in diverse environments, each with different components and with different component versions. To ensure the system builds correctly for all deployable combinations (or, configurations), developers often perform compatibility testing by building their systems on various configurations. However, due to the large number of possible configurations, testing all configurations is often infeasible, and in practice, only a handful of popular configurations are tested; as a result, errors can escape to the field. This problem is compounded when components evolve over time and when test resources are limited. To address these problems, in this dissertation I introduce a process, algorithms and a tool called Rachet. First, I describe a formal modeling scheme for capturing the system configuration space, and a sampling criterion that determines the portion of the space to test. I describe an algorithm to sample configurations satisfying the sampling criterion and methods to test the sampled configurations. Second, I present an approach that incrementally tests compatibility between components, so as to accommodate component evolution. I describe methods to compute test obligations, and algorithms to produce configurations that test the obligations, attempting to reuse test artifacts. Third, I present an approach that prioritizes and tests configurations based on developers' preferences. Configurations are tested, by default starting from the most preferred one as requested by a developer, but cost-related factors are also considered to reduce overall testing time. The testing approaches presented are applied to two large-scale systems in the high-performance computing domain, and experimental results show that the approaches can (1) identify compatibility between components effectively and efficiently, (2) make the process of compatibility testing more practical under constant component evolution, and also (3) help developers achieve preferred compatibility results early in the overall testing process when time and resources are limited

Design and implementation of a routing algorithm to maximize test coverage of permanent faults in FPGAs

Nowadays electronic devices are used in a huge number of applications, from entertainment market to military equipment, from mobile phones to satellites. Each application has its own requirements and constraints depending on its purpose. One particular kind of applications is the one called mission critical that is characterized by a large amount of money that could be lost if something goes wrong. As an example this is the case of satellites that cannot be repaired or returned for maintenance if some parts stop working. When electronic device, and in particular FPGAs, are used in mission critical applications their reliability requires a special attention, therefore a key aspect of them is the capability to tolerate faults. When FPGAs operate in harsh environment, like in space, both temporary and permanent faults can occur due to radiation. The on-line testing technique involves a testing circuit that is capable to test its own used resources. In this work a design and implementation of a routing algorithm to maximize fault coverage of permanent faults is presented

Doctor of Philosophy

dissertationAsynchronous design has a very promising potential even though it has largely received a cold reception from industry. Part of this reluctance has been due to the necessity of custom design languages and computer aided design (CAD) flows to design, optimize, and validate asynchronous modules and systems. Next generation asynchronous flows should support modern programming languages (e.g., Verilog) and application specific integrated circuits (ASIC) CAD tools. They also have to support multifrequency designs with mixed synchronous (clocked) and asynchronous (unclocked) designs. This work presents a novel relative timing (RT) based methodology for generating multifrequency designs using synchronous CAD tools and flows. Synchronous CAD tools must be constrained for them to work with asynchronous circuits. Identification of these constraints and characterization flow to automatically derive the constraints is presented. The effect of the constraints on the designs and the way they are handled by the synchronous CAD tools are analyzed and reported in this work. The automation of the generation of asynchronous design templates and also the constraint generation is an important problem. Algorithms for automation of reset addition to asynchronous circuits and power and/or performance optimizations applied to the circuits using logical effort are explored thus filling an important hole in the automation flow. Constraints representing cyclic asynchronous circuits as directed acyclic graphs (DAGs) to the CAD tools is necessary for applying synchronous CAD optimizations like sizing, path delay optimizations and also using static timing analysis (STA) on these circuits. A thorough investigation for the requirements of cycle cutting while preserving timing paths is presented with an algorithm to automate the process of generating them. A large set of designs for 4 phase handshake protocol circuit implementations with early and late data validity are characterized for area, power and performance. Benchmark circuits with automated scripts to generate various configurations for better understanding of the designs are proposed and analyzed. Extension to the methodology like addition of scan insertion using automatic test pattern generation (ATPG) tools to add testability of datapath in bundled data asynchronous circuit implementations and timing closure approaches are also described. Energy, area, and performance of purely asynchronous circuits and circuits with mixed synchronous and asynchronous blocks are explored. Results indicate the benefits that can be derived by generating circuits with asynchronous components using this methodology

Improving timing verification and delay testing methodologies for IC designs

textThe task of ensuring the correct temporal behavior of IC designs, both before and after fabrication, is extremely important. It is becoming even more imperative as the demand for performance increases and process technology advances into the deep sub-micron region. This dissertation tackles the key issues in the timing verification and delay testing methodologies. An efficient methodology is presented to identify false timing paths in the timing verification methodology which utilizes ATPG technique and timing information from an ordered list of timing paths according to the delay information. This dissertation also presents a speed binning methodology which utilizes structural delay tests successfully instead of functional tests. In addition, it establishes a methodology which quantifies the correlation between the timing verification prediction and actual silicon measurement of timing paths. This quantification methodology lays the foundation for further research to study the impact of deep submicron effects on design performanceElectrical and Computer Engineerin

Improving rewiring scheme and its applications on various circuit design problems.

Lo Wing Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract --- p.iChapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Backgrounds and Definitions --- p.5Chapter 2.1.1 --- Boolean Network --- p.5Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6Chapter 2.1.5 --- Mandatory Assignments --- p.8Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Overview of FIRE --- p.15Chapter 3.3 --- Alternative Wire Identification Method --- p.17Chapter 3.3.1 --- Identifying Candidate Wires --- p.17Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21Chapter 3.5 --- Experimental Results --- p.26Chapter 3.6 --- Conclusions --- p.28Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33Chapter 4.4 --- Experimental Results --- p.37Chapter 4.5 --- Conclusions --- p.43Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45Chapter 5.1 --- Introduction --- p.45Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47Chapter 5.2.1 --- Problem Formulation --- p.47Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51Chapter 5.4 --- Experimental Results --- p.54Chapter 5.5 --- Conclusions --- p.57Chapter 6 --- Conclusions and Future Works --- p.58Bibliography --- p.6

Doctor of Philosophy

dissertationThe design of integrated circuit (IC) requires an exhaustive verification and a thorough test mechanism to ensure the functionality and robustness of the circuit. This dissertation employs the theory of relative timing that has the advantage of enabling designers to create designs that have significant power and performance over traditional clocked designs. Research has been carried out to enable the relative timing approach to be supported by commercial electronic design automation (EDA) tools. This allows asynchronous and sequential designs to be designed using commercial cad tools. However, two very significant holes in the flow exist: the lack of support for timing verification and manufacturing test. Relative timing (RT) utilizes circuit delay to enforce and measure event sequencing on circuit design. Asynchronous circuits can optimize power-performance product by adjusting the circuit timing. A thorough analysis on the timing characteristic of each and every timing path is required to ensure the robustness and correctness of RT designs. All timing paths have to conform to the circuit timing constraints. This dissertation addresses back-end design robustness by validating full cyclical path timing verification with static timing analysis and implementing design for testability (DFT). Circuit reliability and correctness are necessary aspects for the technology to become commercially ready. In this study, scan-chain, a commercial DFT implementation, is applied to burst-mode RT designs. In addition, a novel testing approach is developed along with scan-chain to over achieve 90% fault coverage on two fault models: stuck-at fault model and delay fault model. This work evaluates the cost of DFT and its coverage trade-off then determines the best implementation. Designs such as a 64-point fast Fourier transform (FFT) design, an I2C design, and a mixed-signal design are built to demonstrate power, area, performance advantages of the relative timing methodology and are used as a platform for developing the backend robustness. Results are verified by performing post-silicon timing validation and test. This work strengthens overall relative timed circuit flow, reliability, and testability