Digital instrumentation for the measurement of high spectral purity signals

Improvements on electronic technology in recent years have allowed the application of digital techniques in time and frequency metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. The Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs), as the system front-end, set the ultimate performance of the system in terms of noise. The noise characterization of these components will allow performing punctual considerations on the study of the implementation feasibility of new techniques and for the selection of proper components according to the application requirements. Moreover, most commercial platforms based on FPGA are clocked by quartz oscillators whose accuracy and frequency stability are not suitable for many time and frequency applications. In this case, it is possible to take advantage of the internal Phase Locked Loop (PLL) for generating the internal clock from an external frequency reference. However, the PLL phase noise could degrade the oscillator stability thereby limiting the entire system performance becoming a critical component for digital instrumentation. The information available currently in literature, describes in depth the features of these devices at frequency offsets far from the carrier. However, the information close to the carrier is a more important concern for time and frequency applications. In this frame, my PhD work is focused on understanding the limitations of the critical blocks of digital instrumentation for time and frequency metrology. The aim is to characterize the noise introduced by these blocks and in this manner to be able to predict their effects on a specific application. This is done by modeling the noise introduced by each component and by describing them in terms of general and technical parameters. The parameters of the models are identified and extracted through the corresponding method proposed accordingly to the component operation. This work was validated by characterizing a commercially available platform, Red Pitaya. This platform is an open source embedded system whose resolution and speed (14 bit, 125 MSps) are reasonably close to the state of the art of ADCs and DACs (16 bit, 350 MSps or 14 bit, 1 GSps/3GSPs) and it is potentially sufficient for the implementation of a complete instrument. The characterization results lead to the noise limitations of the platform and give a guideline for instrumentation design techniques. Based on the results obtained from the noise characterization, the implementation of a digital instrument for frequency transfer using fiber link was performed on the Red Pitaya platform. In this project, a digital implementation for the detection and compensation of the phase noise induced by the fiber is proposed. The beat note, representing the fiber length variations, is acquired directly with a high speed ADC followed by a fully digital phase detector. Based on the characterization results, it was expected a limitation in the phase noise measurement given by the PLL. First measurements of this implementation were performed using the 150 km-long buried fibers, placed in the same cables between INRiM and the Laboratoire Souterrain de Modane (LSM) on the Italy-France border. The two fibers are joined together at LSM to obtain a 300 km loop with both ends at INRiM. From these results the noise introduced by the digital system was verified in agreement with characterization results. Further test and improvements will be performed for having a finished system which is intended to be used on the Italian Link for Frequency and Time from Turin to Florence that is 642-km long and to its extension in the rest of Italy that is foreseen in the next future. Currently, a higher performance platform is under assessment by applying the tools and concepts developed along the PhD. The purpose of this project is the implementation of a state of the art phasemeter whose architecture is based on the DAC. In order to estimate the ultimate performance of the instrument, the DAC characterization is under development and preliminary measurements are also reported here

A field programmable gate array based modular motion control platform

The expectations from motion control systems have been rising day by day. As the systems become more complex, conventional motion control systems can not achieve to meet all the specifications with optimized results. This creates the necessity of fundamental changes in the infrastructure of the system. Field programmable gate array (FPGA) technology enables the reconfiguration of the digital hardware, thus dissolving the necessity of infrastructural changes for minor manipulations in the hardware even if the system is deployed. An FPGA based hardware system shrinks the size of the hardware hence the cost. FPGAs also provide better power ratings for the systems as well as a more reliable system with improved performance. As a trade off, the development is rather more difficult than software based systems, which also affects the research and development time of the overall system. In this paper a level of abstraction is introduced in order to diminish the requirement of advanced hardware description language (HDL) knowledge for implementing motion control systems thoroughly on an FPGA. The intellectual property library consists of synthesizable hardware modules specifically implemented for motion control purposes. Other parts of a motion control system, like user interface and trajectory generation, are implemented as software functions in order to protect the modularity of the system. There are also several external hardware designs for interfacing and driving various types of actuators

Fractional - order system modeling and its applications

In order to control or operate any system in a closed-loop, it is important to know its behavior in the form of mathematical models. In the last two decades, a fractional-order model has received more attention in system identification instead of classical integer-order model transfer function. Literature shows recently that some techniques on fractional calculus and fractional-order models have been presenting valuable contributions to real-world processes and achieved better results. Such new developments have impelled research into extensions of the classical identification techniques to advanced fields of science and engineering. This article surveys the recent methods in the field and other related challenges to implement the fractional-order derivatives and miss-matching with conventional science. The comprehensive discussion on available literature would help the readers to grasp the concept of fractional-order modeling and can facilitate future investigations. One can anticipate manifesting recent advances in fractional-order modeling in this paper and unlocking more opportunities for research

Calcul approximatif à haute efficacité énergétique pour des applications de l'internet des objets

Reduced width units are ones of the power reduction methods. However such units have been mostly evaluated separately, i.e. not evaluated in a complete applications. In this thesis, we extend the RISC-V processor with reduced width computation and memory units, in which only a number of most significant bits (MSBs), configurable at runtime is active. The energy reduction vs quality of output trade-offs of applications executed with the extended RISC-V are studied. The results indicate that the energy can be reduced by up to 14% for an error ≤ 0.1%. Moreover we propose a generic energy model that includes both software parameters and hardware architecture ones. It allows software and hardware designers to have an early insight into the effects of optimizations on software and/or units.Les unités à taille réduite font partie des méthodes proposées pour la réduction de la consommation d’énergie. Cependant, la plupart de ces unités sont évaluées séparément,c’est-à-dire elles ne sont pas évaluées dans une application complète. Dans cette thèse, des unités à taille réduite pour le calcul et pour l’accès à la mémoire de données, configurables au moment de l’exécution, sont intégrées dans un processeur RISC-V. La réduction d’énergie et la qualité de sortie des applications exécutées sur le processeur RISC-V étendu avec ces unités, sont évaluées. Les résultats indiquent que la consommation d’énergie peut être réduite jusqu’à 14% pour une erreur ≤0.1%. De plus, nous avons proposé un modèle d’énergie générique qui inclut à la fois des paramètres logiciels et architecturaux. Le modèle permet aux concepteurs logiciels et matériels d’avoir un aperçu rapide sur l’impact des optimisations effectuées sur le code source et/ou sur les unités de calcul

Hardware/software co-design of fractal features based fall detection system

Falls are a leading cause of death in older adults and result in high levels of mortality, morbidity and immobility. Fall Detection Systems (FDS) are imperative for timely medical aid and have been known to reduce death rate by 80%. We propose a novel wearable sensor FDS which exploits fractal dynamics of fall accelerometer signals. Fractal dynamics can be used as an irregularity measure of signals and our work shows that it is a key discriminant for classification of falls from other activities of life. We design, implement and evaluate a hardware feature accelerator for computation of fractal features through multi-level wavelet transform on a reconfigurable embedded System on Chip, Zynq device for evaluating wearable accelerometer sensors. The proposed FDS utilises a hardware/software co-design approach with hardware accelerator for fractal features and software implementation of Linear Discriminant Analysis on an embedded ARM core for high accuracy and energy efficiency. The proposed system achieves 99.38% fall detection accuracy, 7.3× speed-up and 6.53× improvements in power consumption, compared to the software only execution with an overall performance per Watt advantage of 47.6×, while consuming low reconfigurable resources at 28.67%

Event-based fractional order control

The present study provides a generalization of event-based control to the field of fractional calculus, combining the benefits brought by the two approaches into an industrial-suitable control strategy. During recent years, control applications based on fractional order differintegral operators have gained more popularity due to their proven superior performance when compared to classical, integer order, control strategies. However, the current industrial setting is not yet prepared to fully adapt to complex fractional order control implementations that require hefty computational resources; needing highly-efficient methods with minimum control effort. The solution to this particular problem lies in combining benefits of event-based control such as resource optimization and bandwidth allocation with the superior performance of fractional order control. Theoretical and implementation aspects are developed in order to provide a generalization of event-based control into the fractional calculus field. Different numerical examples validate the proposed methodology, providing a useful tool, especially for industrial applications where the event-based control is most needed. Several event-based fractional order implementation possibilities are explored, the final result being an event-based fractional order control methodology. (C) 2020 The Authors. Published by Elsevier B.V. on behalf of Cairo University

Embedded Model Control calls for disturbance modeling and rejection

Robust control design is mainly devoted to guaranteeing the closed-loop stability of a model-based control law in the presence of parametric uncertainties. The control law is usually a static feedback law which is derived from a (nonlinear) model using different methodologies. From this standpoint, stability can only be guaranteed by introducing some ignorance coefficients and restricting the feedback control effort with respect to the model-based design. Embedded Model Control shows that, the model-based control law must and can be kept intact in the case of uncertainty, if, under certain conditions, the controllable dynamics is complemented by suitable disturbance dynamics capable of real-time encoding the different uncertainties affecting the ‘embedded model', i.e. the model which is both the design source and the core of the control unit. To be real-time updated the disturbance state is driven by an unpredictable input vector, the noise, which can only be estimated from the model error. The uncertainty-based (or plant-based) design concerns the noise estimator, so as to prevent the model error from conveying uncertainty components (parametric, cross-coupling, neglected dynamics) which are command-dependent and thus prone to destabilizing the controlled plant, into the embedded model. Separation of the components in the low and high frequency domain by the noise estimator itself allows stability recovery and guarantee, and the rejection of low frequency uncertainty components. Two simple case studies endowed with simulated and experimental runs will help to understand the key assets of the methodolog

DESIGN AND IMPLEMENTATION OF FRACTIONAL-ORDER CONTROLLER IN DELTA DOMAIN

In this work, a fractional-order controller (FOC) is designed in a discrete domain using delta operator parameterization. FOC gets rationally approximated using continued fraction expansion (CFE) in the delta domain. Whenever discretization of any continuous-time system takes place, the choice of sampling time becomes the most critical parameter to get most accurate results. Obtaining a higher sampling rate using conventional shift operator parameterization is not possible and delta operator parameterized discretize time system takes the advantages to circumvent the problem associated with the shift operator parameterization at a high sampling limit. In this work, a first-order plant with delay is considered to be controlled with FOC, and is implemented in discrete delta domain. The plant model is designed using MATLAB as well as in hardware. The fractional-order controller is tuned in the continuous domain and discretized in delta domain to make the discrete delta FOC. Continuous time fractional order operator (s±α) is directly discretized in delta domain to get the overall FOC in discrete domain. The designed controller in implemented using MATLABSimulink and dSPACE board such that dSPACEboard acts as the hardware implemented FOC. The step response characteristics of the closed-loop system using delta domain FOC resembles to that of the results obtained by continuous time controller. It proves that at a high sampling rate, the continuous-time result and discrete-time result are obtained hand to hand rather than the two individual cases. Therefore, the analysis and design of FOC parameterized with delta operator opens up a new area in the design and implementation of discrete FOC, which unifies both continuous and discrete-time results. The discrete model performance characteristics are evaluated in software simulation using MATLAB, and results are validated through the hardware implementation using dSPACE