A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Heterogeneous 2.5D integration on through silicon interposer

© 2015 AIP Publishing LLC. Driven by the need to reduce the power consumption of mobile devices, and servers/data centers, and yet continue to deliver improved performance and experience by the end consumer of digital data, the semiconductor industry is looking for new technologies for manufacturing integrated circuits (ICs). In this quest, power consumed in transferring data over copper interconnects is a sizeable portion that needs to be addressed now and continuing over the next few decades. 2.5D Through-Si-Interposer (TSI) is a strong candidate to deliver improved performance while consuming lower power than in previous generations of servers/data centers and mobile devices. These low-power/high-performance advantages are realized through achievement of high interconnect densities on the TSI (higher than ever seen on Printed Circuit Boards (PCBs) or organic substrates), and enabling heterogeneous integration on the TSI platform where individual ICs are assembled at close proximity

Study of the impact of lithography techniques and the current fabrication processes on the design rules of tridimensional fabrication technologies

Working for the photolithography tool manufacturer leader sometimes gives me the impression of how complex and specific is the sector I am working on. This master thesis topic came with the goal of getting the overall picture of the state-of-the-art: stepping out and trying to get a helicopter view usually helps to understand where a process is in the productive chain, or what other firms and markets are doing to continue improvingUniversidad de sevilla.Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico

Implementation and Characterisation of Monolithic CMOS Pixel Sensors for the CLIC Vertex and Tracking Detectors

Different CMOS technologies are being considered for the vertex and tracking layers of the detector at the proposed high-energy e$^{+}$e$^{−}$ Compact Linear Collider (CLIC). CMOS processes have been proven to be suitable for building high granularity, large area detector systems with low material budget and low power consumption. An effort is put on implementing detectors capable of performing precise timing measurements. Two Application-Specific Integrated Circuits (ASICs) for particle detection have been developed in the framework of this thesis, following the specifications of the CLIC vertex and tracking detectors. The process choice was based on a study of the features of each of the different available technologies and an evaluation of their suitability for each application. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a pixelated detector chip designed to be used in capacitively coupled assemblies with the CLICpix2 readout chip, in the framework of the vertex detector at CLIC. The chip comprises a matrix of 128×128 square pixels with 25 µm pitch. A commercial 180 nm High-Voltage (HV) CMOS process was used for the C3PD design. The charge is collected with a large deep N-well, while each pixel includes a preamplifier placed on top of the collecting electrode. The C3PD chip was produced on wafers with different values for the substrate resistivity (∼ 20, 80, 200 and 1000 Ωcm) and has been extensively tested through laboratory measurements and beam tests. The design details and characterisation results of the C3PD chip will be presented. The CLIC Tracker Detector (CLICTD) is a novel monolithic detector chip developed in the context of the silicon tracker at CLIC. The CLICTD chip combines high density, mixed mode circuits on the same substrate, while it performs a fast time-tagging measurement with 10 ns time bins. The chip is produced in a 180 nm CMOS imaging process with a High-Resistivity (HR) epitaxial layer. A matrix of 16×128 detecting cells, each measuring 300 × 30 µm$^{2}$ , is included. A small N-well is used to collect the charge generated in the sensor volume, while an additional deep N-type implant is used to fully deplete the epitaxial layer. Using a process split, additional wafers are produced with a segmented deep N-type implant, a modification that has been simulated to result in a faster charge collection time. Each detecting cell is segmented into eight front-ends to ensure prompt charge collection in the sensor diodes. A simultaneous 8-bit timing and 5-bit energy measurement is performed in each detecting cell. A detailed description of the CLICTD design will be given, followed by the first measurement results

Caractérisation électrique et modélisation du transport dans matériaux et dispositifs SOI avancés

This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres

Topical Workshop on Electronics for Particle Physics

The purpose of the workshop was to present results and original concepts for electronics research and development relevant to particle physics experiments as well as accelerator and beam instrumentation at future facilities; to review the status of electronics for the LHC experiments; to identify and encourage common efforts for the development of electronics; and to promote information exchange and collaboration in the relevant engineering and physics communities