Optimal competitiveness for the Rectilinear Steiner Arborescence problem

We present optimal online algorithms for two related known problems involving Steiner Arborescence, improving both the lower and the upper bounds. One of them is the well studied continuous problem of the {\em Rectilinear Steiner Arborescence} ($RSA$). We improve the lower bound and the upper bound on the competitive ratio for $RSA$ from $O(\log N)$ and $\Omega(\sqrt{\log N})$ to $\Theta(\frac{\log N}{\log \log N})$, where $N$ is the number of Steiner points. This separates the competitive ratios of $RSA$ and the Symetric-$RSA$, two problems for which the bounds of Berman and Coulston is STOC 1997 were identical. The second problem is one of the Multimedia Content Distribution problems presented by Papadimitriou et al. in several papers and Charikar et al. SODA 1998. It can be viewed as the discrete counterparts (or a network counterpart) of $RSA$. For this second problem we present tight bounds also in terms of the network size, in addition to presenting tight bounds in terms of the number of Steiner points (the latter are similar to those we derived for $RSA$)

Interconnect tree optimization algorithm in nanometer very large scale integration designs

This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime

Shortest Paths and Steiner Trees in VLSI Routing

Routing is one of the major steps in very-large-scale integration (VLSI) design. Its task is to find disjoint wire connections between sets of points on a chip, subject to numerous constraints. This problem is solved in a two-stage approach, which consists of so-called global and detailed routing steps. For each set of metal components to be connected, global routing reduces the search space by computing corridors in which detailed routing sequentially determines the desired connections as shortest paths. In this thesis, we present new theoretical results on Steiner trees and shortest paths, the two main mathematical concepts in routing. In the practical part, we give computational results of BonnRoute, a VLSI routing tool developed at the Research Institute for Discrete Mathematics at the University of Bonn. Interconnect signal delays are becoming increasingly important in modern chip designs. Therefore, the length of paths or direct delay measures should be taken into account when constructing rectilinear Steiner trees. We consider the problem of finding a rectilinear Steiner minimum tree (RSMT) that --- as a secondary objective --- minimizes a signal delay related objective. Given a source we derive some structural properties of RSMTs for which the weighted sum of path lengths from the source to the other terminals is minimized. Also, we present an exact algorithm for constructing RSMTs with weighted sum of path lengths as secondary objective, and a heuristic for various secondary objectives. Computational results for industrial designs are presented. We further consider the problem of finding a shortest rectilinear Steiner tree in the plane in the presence of rectilinear obstacles. The Steiner tree is allowed to run over obstacles; however, if it intersects an obstacle, then no connected component of the induced subtree must be longer than a given fixed length. This kind of length restriction is motivated by its application in VLSI routing where a large Steiner tree requires the insertion of repeaters which must not be placed on top of obstacles. We show that there are optimal length-restricted Steiner trees with a special structure. In particular, we prove that a certain graph (called augmented Hanan grid) always contains an optimal solution. Based on this structural result, we give an approximation scheme for the special case that all obstacles are of rectangular shape or are represented by at most a constant number of edges. Turning to the shortest paths problem, we present a new generic framework for Dijkstra's algorithm for finding shortest paths in digraphs with non-negative integral edge lengths. Instead of labeling individual vertices, we label subgraphs which partition the given graph. Much better running times can be achieved if the number of involved subgraphs is small compared to the order of the original graph and the shortest path problems restricted to these subgraphs is computationally easy. As an application we consider the VLSI routing problem, where we need to find millions of shortest paths in partial grid graphs with billions of vertices. Here, the algorithm can be applied twice, once in a coarse abstraction (where the labeled subgraphs are rectangles), and once in a detailed model (where the labeled subgraphs are intervals). Using the result of the first algorithm to speed up the second one via goal-oriented techniques leads to considerably reduced running time. We illustrate this with the routing program BonnRoute on leading-edge industrial chips. Finally, we present computational results of BonnRoute obtained on real-world VLSI chips. BonnRoute fulfills all requirements of modern VLSI routing and has been used by IBM and its customers over many years to produce more than one thousand different chips. To demonstrate the strength of BonnRoute as a state-of-the-art industrial routing tool, we show that it performs excellently on all traditional quality measures such as wire length and number of vias, but also on further criteria of equal importance in the every-day work of the designer

Algorithms for cartographic visualization

Maps are effective tools for communicating information to the general public and help people to make decisions in, for example, navigation, spatial planning and politics. The mapmaker chooses the details to put on a map and the symbols to represent them. Not all details need to be geographic: thematic maps, which depict a single theme or attribute, such as population, income, crime rate, or migration, can very effectively communicate the spatial distribution of the visualized attribute. The vast amount of data currently available makes it infeasible to design all maps manually, and calls for automated cartography. In this thesis we presented efficient algorithms for the automated construction of various types of thematic maps. In Chapter 2 we studied the problem of drawing schematic maps. Schematic maps are a well-known cartographic tool; they visualize a set of nodes and edges (for example, highway or metro networks) in simplified form to communicate connectivity information as effectively as possible. Many schematic maps deviate substantially from the underlying geography since edges and vertices of the original network are moved in the simplification process. This can be a problem if we want to integrate the schematized network with a geographic map. In this scenario the schematized network has to be drawn with few orientations and links, while critical features (cities, lakes, etc.) of the base map are not obscured and retain their correct topological position with respect to the network. We developed an efficient algorithm to compute a collection of non-crossing paths with fixed orientations using as few links as possible. This algorithm approximates the optimal solution to within a factor that depends only on the number of allowed orientations. We can also draw the roads with different thicknesses, allowing us to visualize additional data related to the roads such as trafic volume. In Chapter 3 we studied methods to visualize quantitative data related to geographic regions. We first considered rectangular cartograms. Rectangular cartograms represent regions by rectangles; the positioning and adjacencies of these rectangles are chosen to suggest their geographic locations to the viewer, while their areas are chosen to represent the numeric values being communicated by the cartogram. One drawback of rectangular cartograms is that not every rectangular layout can be used to visualize all possible area assignments. Rectangular layouts that do have this property are called area-universal. We show that area-universal layouts are always one-sided, and we present algorithms to find one-sided layouts given a set of adjacencies. Rectangular cartograms often provide a nice visualization of quantitative data, but cartograms deform the underlying regions according to the data, which can make the map virtually unrecognizable if the data value differs greatly from the original area of a region or if data is not available at all for a particular region. A more direct method to visualize the data is to place circular symbols on the corresponding region, where the areas of the symbols correspond to the data. However, these maps, so-called symbol maps, can appear very cluttered with many overlapping symbols if large data values are associated with small regions. In Chapter 4 we proposed a novel type of quantitative thematic map, called necklace map, which overcomes these limitations. Instead of placing the symbols directly on a region, we place the symbols on a closed curve, the necklace, which surrounds the map. The location of a symbol on the necklace should be chosen in such a way that the relation between symbol and region is as clear as possible. Necklace maps appear clear and uncluttered and allow for comparatively large symbol sizes. We developed algorithms to compute necklace maps and demonstrated our method with experiments using various data sets and maps. In Chapter 5 and 6 we studied the automated creation of ow maps. Flow maps are thematic maps that visualize the movement of objects, such as people or goods, between geographic regions. One or more sources are connected to several targets by lines whose thickness corresponds to the amount of ow between a source and a target. Good ow maps reduce visual clutter by merging (bundling) lines smoothly and by avoiding self-intersections. We developed a new algorithm for drawing ow trees, ow maps with a single source. Unlike existing methods, our method merges lines smoothly and avoids self-intersections. Our method is based on spiral trees, a new type of Steiner trees that we introduced. Spiral trees have an angle restriction which makes them appear smooth and hence suitable for drawing ow maps. We study the properties of spiral trees and give an approximation algorithm to compute them. We also show how to compute ow trees from spiral trees and we demonstrate our approach with extensive experiments

Timing-Constrained Global Routing with Buffered Steiner Trees

This dissertation deals with the combination of two key problems that arise in the physical design of computer chips: global routing and buffering. The task of buffering is the insertion of buffers and inverters into the chip's netlist to speed-up signal delays and to improve electrical properties of the chip. Insertion of buffers and inverters goes alongside with construction of Steiner trees that connect logical sources with possibly many logical sinks and have buffers and inverters as parts of these connections. Classical global routing focuses on packing Steiner trees within the limited routing space. Buffering and global routing have been solved separately in the past. In this thesis we overcome the limitations of the classical approaches by considering the buffering problem as a global, multi-objective problem. We study its theoretical aspects and propose algorithms which we implement in the tool BonnRouteBuffer for timing-constrained global routing with buffered Steiner trees. At its core, we propose a new theoretically founded framework to model timing constraints inherently within global routing. As most important sub-task we have to compute a buffered Steiner tree for a single net minimizing the sum of prices for delays, routing congestion, placement congestion, power consumption, and net length. For this sub-task we present a fully polynomial time approximation scheme to compute an almost-cheapest Steiner tree with a given routing topology and prove that an exact algorithm cannot exist unless P=NP. For topology computation we present a bicriteria approximation algorithm that bounds both the geometric length and the worst slack of the topology. To improve the practical results we present many heuristic modifications, speed-up- and post-optimization techniques for buffered Steiner trees. We conduct experiments on challenging real-world test cases provided by our cooperation partner IBM to demonstrate the quality of our tool. Our new algorithm could produce better solutions with respect to both timing and routability. After post-processing with gate sizing and Vt-assignment, we can even reduce the power consumption on most instances. Overall, our results show that our tool BonnRouteBuffer for timing-constrained global routing is superior to industrial state-of-the-art tools

An integrated placement and routing approach

As the feature size continues scaling down, interconnects become the major contributor of signal delay. Since interconnects are mainly determined by placement and routing, these two stages play key roles to achieve high performance. Historically, they are divided into two separate stages to make the problem tractable. Therefore, the routing information is not available during the placement process. Net models such as HPWL, are employed to approximate the routing to simplify the placement problem. However, the good placement in terms of these objectives may not be routable at all in the routing stage because different objectives are optimized in placement and routing stages. This inconsistancy makes the results obtained by the two-step optimization method far from optimal;In order to achieve high-quality placement solution and ensure the following routing, we propose an integrated placement and routing approach. In this approach, we integrate placement and routing into the same framework so that the objective optimized in placement is the same as that in routing. Since both placement and routing are very hard problems (NP-hard), we need to have very efficient algorithms so that integrating them together will not lead to intractable complexity;In this dissertation, we first develop a highly efficient placer - FastPlace 3.0 for large-scale mixed-size placement problem. Then, an efficient and effective detailed placer - FastDP is proposed to improve global placement by moving standard cells in designs. For high-degree nets in designs, we propose a novel performance-driven topology design algorithm to generate good topologies to achieve very strict timing requirement. In the routing phase, we develop two global routers, FastRoute and FastRoute 2.0. Compared to traditional global routers, they can generate better solutions and are two orders of magnitude faster. Finally, based on these efficient and high-quality placement and routing algorithms, we propose a new flow which integrates placement and routing together closely. In this flow, global routing is extensively applied to obtain the interconnect information and direct the placement process. In this way, we can get very good placement solutions with guaranteed routability

Rectilinear Steiner Tree Construction

The Minimum Rectilinear Steiner Tree (MRST) problem is to find the minimal spanning tree of a set of points (also called terminals) in the plane that interconnects all the terminals and some extra points (called Steiner points) introduced by intermediate junctions, and in which edge lengths are measured in the L1 (Manhattan) metric. This is one of the oldest optimization problems in mathematics that has been extensively studied and has been proven to be NP-complete, thus efficient approximation heuristics are more applicable than exact algorithms. In this thesis, we present a new heuristic to construct rectilinear Steiner trees (RSTs) with a close approximation of minimum length in Ο(n log n) time. To this end, we recursively divide a plane into a set of sub-planes of which optimal rectilinear Steiner trees (optRSTs) can be generated by a proposed exact algorithm called Const_optRST. By connecting all the optRSTs of the sub-planes, a sub-optimal MRST is eventually constructed. We show experimentally that for topologies with up to 100 terminals, the heuristic is 1.06 to 3.45 times faster than RMST, which is an efficient algorithm based on Prim’s method, with accuracy improvements varying from 1.31 % to 10.21 %

Approximation Complexity of Optimization Problems : Structural Foundations and Steiner Tree Problems

In this thesis we study the approximation complexity of the Steiner Tree Problem and related problems as well as foundations in structural complexity theory. The Steiner Tree Problem is one of the most fundamental problems in combinatorial optimization. It asks for a shortest connection of a given set of points in an edge-weighted graph. This problem and its numerous variants have applications ranging from electrical engineering, VLSI design and transportation networks to internet routing. It is closely connected to the famous Traveling Salesman Problem and serves as a benchmark problem for approximation algorithms. We give a survey on the Steiner tree Problem, obtaining lower bounds for approximability of the (1,2)-Steiner Tree Problem by combining hardness results of Berman and Karpinski with reduction methods of Bern and Plassmann. We present approximation algorithms for the Steiner Forest Problem in graphs and bounded hypergraphs, the Prize Collecting Steiner Tree Problem and related problems where prizes are given for pairs of terminals. These results are based on the Primal-Dual method and the Local Ratio framework of Bar-Yehuda. We study the Steiner Network Problem and obtain combinatorial approximation algorithms with reasonable running time for two special cases, namely the Uniform Uncapacitated Case and the Prize Collecting Uniform Uncapacitated Case. For the general case, Jain's algorithms obtains an approximation ratio of 2, based on the Ellipsoid Method. We obtain polynomial time approximation schemes for the Dense Prize Collecting Steiner Tree Problem, Dense k-Steiner Problem and the Dense Class Steiner Tree Problem based on the methods of Karpinski and Zelikovsky for approximating the Dense Steiner Tree Problem. Motivated by the question which parameters make the Steiner Tree problem hard to solve, we make an excurs into Fixed Parameter Complexity, focussing on structural aspects of the W-Hierarchy. We prove a Speedup Theorem for the classes FPT and SP and versions if Levin's Lower Bound Theorem for the class SP as well as for Randomized Space Complexity. Starting from the approximation schemes for the dense Steiner Tree problems, we deal with the efficiency of polynomial time approximation schemes in general. We separate the class EPTAS from PTAS under some reasonable complexity theoretic assumption. The same separation was achieved by Cesaty and Trevisan under some assumtion from Fixed Parameter Complexity. We construct an oracle under which our assumtion holds but that of Cesati and Trevisan does not, which implies that using relativizing proof techniques one cannot show that our assumption implies theirs