A study of silicon and germanium junctionless transistors

Technology boosters, such as strain, HKMG and FinFET, have been introduced into semiconductor industry to extend Moore’s law beyond 130 nm technology nodes. New device structures and channel materials are highly demanded to keep performance enhancement when the device scales beyond 22 nm. In this work, the properties and feasibility of the proposed Junctionless transistor (JNT) have been evaluated for both Silicon and Germanium channels. The performance of Silicon JNTs with 22 nm gate length have been characterized at elevated temperature and stressed conditions. Furthermore, steep Subthreshold Slopes (SS) in JNT and IM devices are compared. It is observed that the floating body in JNT is relatively dynamic comparing with that in IM devices and proper design of the device structure may further reduce the VD for a sub- 60 mV/dec subthreshold slope. Diode configuration of the JNT has also been evaluated, which demonstrates the first diode without junctions. In order to extend JNT structure into the high mobility material Germanium (Ge), a full process has been develop for Ge JNT. Germanium-on-Insulator (GeOI) wafers were fabricated using Smart-Cut with low temperature direct wafer bonding method. Regarding the lithography and pattern transfer, a top-down process of sub-50-nm width Ge nanowires is developed in this chapter and Ge nanowires with 35 nm width and 50 nm depth are obtained. The oxidation behaviour of Ge by RTO has been investigated and high-k passivation scheme using thermally grown GeO2 has been developed. With all developed modules, JNT with Ge channels have been fabricated by the CMOScompatible top-down process. The transistors exhibit the lowest subthreshold slope to date for Ge JNT. The devices with a gate length of 3 μm exhibit a SS of 216 mV/dec with an ION/IOFF current ratio of 1.2×103 at VD = -1 V and DIBL of 87 mV/V

Investigation on Performance Metrics of Nanoscale Multigate MOSFETs towards RF and IC Applications

Silicon-on-Insulator (SOI) MOSFETs have been the primary precursor for the CMOS technology since last few decades offering superior device performance in terms of package density, speed, and reduced second order harmonics. Recent trends of investigation have stimulated the interest in Fully Depleted (FD) SOI MOSFET because of their remarkable scalability efficiency. However, some serious issues like short channel effects (SCEs) viz drain induced barrier lowering (DIBL), Vth roll-off, subthreshold slope (SS), and hot carrier effects (HCEs) are observed in nanoscale regime. Numerous advanced structures with various engineering concepts have been addressed to reduce the above mentioned SCEs in SOI platform. Among them strain engineering, high-k gate dielectric with metal gate technology (HKMG), and non-classical multigate technologies are most popular models for enhancement in carrier mobility, suppression of gate leakage current, and better immunization to SCEs. In this thesis, the performance of various emerging device designs are analyzed in nanoscale with 2-D modeling as well as through calibrated TCAD simulation. These attempts are made to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices. Various MOS parameters like gate work function (_m), channel length (L), channel thickness (tSi), and gate oxide thickness (tox) are optimized for both FD-SOI and Multiple gate technology. As the semiconductor industries migrate towards multigate technology for system-on-chip (SoC), system-in-package (SiP), and internet-of-things (IoT) applications, an appropriate examination of the advanced multiple gate MOFETs is required for the analog/RF application keeping reliability issue in mind. Various non-classical device structures like gate stack engineering and halo doping in the channel are extensively studied for analog/RF applications in double gate (DG) platform. A unique attempt has been made for detailed analysis of the state-of-the-art 3-D FinFET on dependency of process variability. The 3-D architecture is branched as Planar or Trigate or FinFET according to the aspect ratio (WFin=HFin). The evaluation of zero temperature coefficient (ZTC) or temperature inflection point (TCP) is one of the key investigation of the thesis for optimal device operation and reliability. The sensitivity of DG-MOSFET and FinFET performances have been addressed towards a wide range of temperature variations, and the ZTC points are identified for both the architectures. From the presented outcomes of this work, some ideas have also been left for the researchers for design of optimum and reliable device architectures to meet the requirements of high performance (HP) and/or low standby power (LSTP) applications

Simulation of FinFET Structures

The intensive downscaling of MOS transistors has been the major driving force behind the aggressive increases in transistor density and performance, leading to more chip functionality at higher speeds. While on the other side the reduction in MOSFET dimensions leads to the close proximity between source and drain, which in turn reduces the ability of the gate electrode to control the potential distribution and current flow in the channel region and also results in some undesirable effects called the short-channel effects. These limitations associated with downscaling of MOSFET device geometries have lead device designers and researchers to number of innovative techniques which include the use of different device structures, different channel materials, different gate-oxide materials, different processes such as shallow trench isolation, source/drain silicidation, lightly doped extensions etc. to enable controlled device scaling to smaller dimensions. A lot of research and development works have been done in these and related fields and more remains to be carried out in order to exploit these devices for the wider applications

Design and performance analysis of Tri-gate GaN HEMTs

GaN-based high electron mobility transistors (HEMT) are promising devices for radio frequency (RF) and high-power electronics and are already in use for RF power amplifiers and for power switches. Commonly, these devices are normally-on transistors, i.e., they are in the on-state at zero applied gate voltage, what limits their suitability for various applications, such as fail-safe power switches and RF amplifiers with single-polarity power supply. Unfortunately, in contrast to GaAs- and InP HEMTs, achieving normally-off operation, i.e., a positive thresh-old voltage, for GaN heterostructures is difficult due to the high density of the polarization-induced two-dimensional electron gas (2DEG) at the barrier/buffer interface. For fast RF HEMTs, short gates are required. However, HEMTs with aggres-sively scaled gate length frequently suffer from short-channel effects caused by a degraded control of the gate over the channel. This leads to a deterioration of the transistors off-state performance (increased subthreshold swing and drain-induced barrier lowering) and on-state behavior (increased drain conductance). The tri-gate design has recently been applied to MOSFETs and HEMTs to improve the gate control and suppress short channel effects. Experimental tri-gate transistors show excellent down-scaling characteristics, improved performance, and, in particular for GaN tri-gate HEMTs, a significant shift of the threshold voltage toward positive values. On the other hand, tri-gate GaN normally-off HEMTs are still suffering from increased parasitics causing degraded RF performance (particularly in terms of cutoff frequency) compared to their planar counterparts. Improving the RF performance of GaN tri-gate HEMTs by reducing the parasitics is essential, but this requires a deep understanding of device physics and a thorough analysis of the root causes. In the present work, in-depth theoretical investigations of GaN tri-gate HEMT operation are performed and extensive simulation studies for these devices are conducted. As a result of these efforts, improved insights in the physics of GaN tri-gate HEMTs are achieved, the potential of this transistor type is assessed, design guidelines are elaborated, and advantageous designs are developed. It is shown that the 2DEG sheet density decreases by shrinking the body width, that the threshold voltage of GaN tri-gate HEMTs strongly depends on the width of AlGaN/GaN bodies, and that solely by decreasing the body width a transition from normally-on to normally-off operation can be achieved. The separation between adjacent bodies is shown to have less impact on threshold voltage. The results also show that for wide bodies (> 200 nm) the channel is controlled by both the top-gate and the sidewall gates, while for decreasing body width the control by top-gate gradually diminishes and the channel will be only controlled by side-gates. Furthermore, the impact of AlGaN barrier design (Al content, thickness) is studied, and the results show a limited dependency of the threshold voltage on the barrier design for very narrow bodies. The tri-gate concept enables normally-off operation, provides improved on-state performance (higher transconductance), and effectively suppresses short-channel effects in the off-state. Moreover, the simulation results show that GaN tri-gate HEMTs can exhibit higher breakdown voltages and operate closer to the theoretical limit for GaN devices than their planar counterparts. Moreover, the simulations indicate that the RF performance of GaN tri-gate HEMTs with optimized body designs can be superior to that of conventional planar devices. A means to improve the RF performance is the reduction of the body etch height, leading to a decreased parasitic coupling between the sidewalls and the source/drain electrodes. Thus, reducing the body height leads to a decreased overall gate capacitance and an improved RF performance. Another way to reduce the overall gate capacitance is to cover the body sidewalls with a dielectric (e.g. SiN). This reduces the fringing capacitance components since the gap between neighboring bodies that is filled with gate metal is narrower compared to the case without dielectrics. Finally, the polarization charge at the barrier/channel interface and thus the electron density in the 2DEG) can be increased either by increasing the aluminium content of the AlGaN barrier or by using a different barrier material (e.g., lattice matched In0.17 Al0.83 N). In the frame of a joint DFG project, GaN tri-gate HEMTs designed based on the improved insights in the physics of these devices have been fabricated and characterized at Fraunhofer IAF. These devices having a gate length of 100 nm are by far the fastest GaN tri-gate HEMTs worldwide and show record performance in terms of cutoff frequency (120 GHz) and maximum frequency of oscillation (300 GHz).HEMTs (high electron mobility transistors) auf GaN-Basis besitzen großes Potenzial für die HF- (Hochfrequenz) und Leistungselektronik und werden bereits in HF-Leistungsverstärkern und als Leistungsschalter verwendet. Üblicherweise sind GaN HEMTs Normally-On Transistoren (d.h. Transistoren, die sich bei einer Gatespannung von 0 V im Ein-Zustand befinden), was für Anwendungen wie Fail-Safe-Leistungsschalter und HF-Verstärker mit nur einer Versorgungsspannung nachteilig ist. Es schwierig, GaN HEMTs mit Normally-Off-Charakteristik (HEMTs mit positiver Schwellspannung) zu realisieren, da in diesen Transistoren die Dichte des sich an der Grenzfläche Barriere/Puffer ausbildenden 2DEG (zweidimensionales Elektronengas) auf Grund starker Polarisationseffekte erheblich größer als in GaAs und InP HEMTs ist. Die Realisierung schneller HF-HEMTs erfordert kurze Gates. Allerdings leiden Transistoren mit sehr kurzen Gates häufig unter Kurzkanaleffekten und einer reduzierten Steuerwirkung des Gates, was zu einer Verschlechterung des Verhaltens im Aus-Zustand (erhöhte Werte für den Subthreshold Swing und das Drain-Induced Barrier Low-ering) und im Ein-Zustand (erhöhter Drainleitwert) führt. In jüngster Zeit wird bei MOSFETs und HEMTs das Tri-Gate-Design angewendet, um die Gatesteuerwirkung zu verbessern und Kurzkanaleffekte zu unterdrücken. So wurden bereits Tri-Gate-Transistoren mit ausgezeichnetem Skalierungsverhalten, verbesserten Eigenschaften und, speziell im Fall von GaN Tri-Gate-HEMTs, positiver Schwellspannung, demonstriert. Auf der anderen Seite leiden GaN Tri-Gate-HEMTs mit Normally-Off-Charakteristik jedoch unter großen Parasitäten, die das HF-Verhalten (insbesondere die Transitfrequenz) beeinträchtigen. Die Verbesserung des HF-Verhaltens und eine Reduzierung der Parasitäten von GaN Tri-Gate-HEMTs ist daher dringend nötig. Das erfordert jedoch ein tiefes Eindringen in die Physik dieser Bauelemente. In der vorliegenden Arbeit werden umfassende theoretische Untersuchungen und Bauelementesimulationen zu GaN Tri-Gate-HEMT beschrieben, die zu einem deutlichen verbesserten Verständnis der Wirkungsweise von GaN Tri-Gate-HEMTs führten. So konnten das Potential dieses Transistortyps bewertet, Designregeln erarbeitet und vorteilhafte Transistordesigns entwickelt werden. In der Arbeit wird gezeigt, dass eine Verringerung der Bodyweite bei gegebener Gatespannung zu einer Verringerung der Ladungsträgerdichte im 2DEG führt, dass die Schwellspannung maßgeblich von der Bodyweite bestimmt wird und dass bei hinreichend geringer Bodyweite der Übergang vom Normall-On- zum Normally-Off-Betrieb erfolgt. Es wird auch gezeigt, dass der Abstand zwischen benachbarten Bodies nur einen geringen Einfluss auf die Schwellspannung hat. Darüber hinaus wird demonstriert, dass im Fall weiter Bodies (> 200 nm) der Kanal sowohl durch das Top-Gate als auch durch die Seiten-Gates gesteuert wird, während bei schmaleren Bodies die Steuerwirkung durch das Top-Gate geringer wird und die Verhältnisse im Kanal im Wesentlichen durch das Seiten-Gates bestimmt werden. In der Arbeit wird weiterhin Rolle des Designs der AlGaN-Barriere (Al-Gehalt, Dicke) untersucht und demonstriert, dass die Gestaltung der Barriere bei schmalen Bodies nur einen begrenzten Einfluss auf die Schwellspannung hat. Die Untersuchungen zeigen deutlich, dass das mit dem Tri-Gate-Konzept Normally-Off-Transistoren realisierbar sind, dass das Transistorverhalten im Ein-Zustand verbessert (höhere Steilheit) wird, und dass Kurzkanaleffekte im Aus-Zustand wirkungsvoll unterdrückt. Es wird auch demonstriert, dass GaN Tri-Gate HEMTs höhere Durchbruchspannungen zeigen und näher an der theoretischen Grenze für GaN-Bauelemente arbeiten als planare GaN HEMTs. Ein weiteres Ergebnis der vorliegenden Arbeit ist der Nachweis, dass GaN Tri-Gate-HEMTs mit sorgfältig optimiertem Design den planaren HEMTs auch hinsichtlich des HF-Verhaltens überlegen sind. Ein Mittel zur Verbesserung des HF-Verhaltens ist die Reduzierung der Body-Ätzhöhe, die zur Verringerung der parasitären Kopplung zwischen den Body-Seitenwänden und den Source/Drain-Elektroden und somit zu einer geringeren Gatekapazität führt. Eine weitere Maßnahme zur Reduzierung der Gatekapazität ist die Beschichtung der Body-Seitenwände mit einem Dielektrikum (z.B. SiN). Das verringert die Streukapazität, da jetzt die mit dem Gatemetall gefüllte Lücken zwischen benachbarten Bodies schmaler sind. Schließlich wird gezeigt, dass die Polarisationsladung an der Grenzfläche Barrier/Kanal und somit die Elektronendichte im 2DEG durch Erhöhung des Al-Gehalts der AlGaN-Barriere oder durch Nutzung eines anderen Materials für die Barriere (z.B. gitterangepasstes In0.17 Al0.83 N) gesteigert werden kann

Novel 3-D IC technology

textFor many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Electrical and Computer Engineerin

Compact DC Modeling of Tunnel-FETs

En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

Compact DC Modeling of Tunnel-FETs

En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

Modeling & Simulation of High Performance Nanoscale MOSFETs

Silicon-on-insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications.A new type of transistor without junctions and no doping concentration gradients is analysed and demonstrated. These device structures address the challenge of short channel effects (SCEs) resulting with scaling of transistor dimensions and higher performance for deep submicron VLSI integration. Recent experimental studies have invigorated interest in partially depleted (PD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. SELBOX structure offer an alternative way of suppressing kink effect and self heating effects in PD-SOI devices with a proper selection of oxide gap length. Also in order to mitigate the difficulties in fabrication of ultra thin devices for the semiconductor industry, resulting from scaling of gate length in MOSFET, a new device structure called junctionless (JL) transistors have recently been reported as an alternative device. In conclusion, extensive numerical simulation studies were used to explore and compare the electrical characteristics of SELBOX SOI MOSFET with a conventional single-material gate (SMG) bulk MOSFET. The proposed work investigates the DC and AC characteristics of the junctionless transistors. Also the performance analysis of JL transistors is compared and presented with the conventional DG MOSFET structure. The results presented in this work are expected to provide incentive for further experimental exploration

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before