127 research outputs found
Design, Modeling and Analysis of Non-classical Field Effect Transistors
Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs.
In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs.
In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization
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Oxygen-insertion Technology for CMOS Performance Enhancement
Until 2003, the semiconductor industry followed Dennard scaling rules to improve complementary metal-oxide-semiconductor (CMOS) transistor performance. However, performance gains with further reductions in transistor gate length are limited by physical effects that do not scale commensurately with device dimensions: short-channel effects (SCE) due to gate-leakage-limited gate-oxide thickness scaling, channel mobility degradation due to enhanced vertical electric fields, increased parasitic resistances due to reductions in source/drain (S/D) contact area, and increased variability in transistor performance due to random dopant fluctuation (RDF) effects and gate work function variations (WFV). These emerging scaling issues, together with increased process complexity and cost, pose severe challenges to maintaining the exponential scaling of transistor dimensions. This dissertation discusses the benefits of oxygen-insertion (OI) technology, a CMOS performance booster, for overcoming these challenges. The benefit of OI technology to mitigate the increase in sheet resistance () with decreasing junction depth () for ultra-shallow-junctions (USJs) relevant for deep-sub-micron planar CMOS transistors is assessed through the fabrication of test structures, electrical characterization, and technology computer-aided design (TCAD) simulations. Experimental and secondary ion mass spectroscopy (SIMS) analyses indicate that OI technology can facilitate low-resistivity USJ formation by reducing and due to retarded transient-enhanced-diffusion (TED) effects and enhanced dopant retention during post-implantation thermal annealing. It is also shown that a low-temperature-oxide (LTO) capping can increase unfavorably due to lower dopant activation levels, which can be alleviated by OI technology. This dissertation extends the evaluation of OI technology to advanced FinFET technology, targeting 7/8-nm low power technology node. A bulk-Si FinFET design comprising a super-steep retrograde (SSR) fin channel doping profile achievable with OI technology is studied by three-dimensional (3-D) TCAD simulations. As compared with the conventional bulk-Si (control) FinFET design with a heavily-doped fin channel doping profile, SSR FinFETs can achieve higher ratios and reduce the sensitivity of device performance to variations due to the lightly doped fin channel. As compared with the SOI FinFET design, SSR FinFETs can achieve similarly low for 6T-SRAM cell yield estimation. Both SSR and SOI design can provide for as much as 100 mV reduction in compared with the control FinFET design. Overall, the SSR FinFET design that can be achieved with OI technology is demonstrated to be a cheaper alternative to the SOI FinFET technology for extending CMOS scaling beyond the 10-nm node. Finally, this dissertation investigates the benefits of OI technology for reducing the Schottky barrier height () of a Pt/Ti/p-type Si metal-semiconductor (M/S) contact, which can be expected to help reduce the specific contact resistivity for a p-type silicon contact. Electrical measurements of back-to-back Schottky diodes, SIMS, and X-ray photoelectron spectroscopy (XPS) show that the reduction in is associated with enhanced Ti 2p and Si 2p core energy level shifts. OI technology is shown to favor low- Pt monosilicide formation during forming gas anneal (FGA) by suppressing the grain boundary diffusion of Pt atoms into the crystalline Si substrate
Developement of simulation tools for the analysis of variability in advanced semiconductor electron devices
The progressive down-scaling has been the driving force behind the integrated circuit (IC) industry for several decades, continuously delivering higher component densities and greater chip functionality, while reducing the cost per function from one CMOS technology generation to the next. Mooreโs law boosts IC industry profits by constantly releasing high-quality and inexpensive electronic applications into the market using new technologies. From the 1 m gate lengths of the eighties to the 35 nm gate lengths of contemporary 22 nm technology, the industry successfully achieved its scaling goals, not only miniaturizing devices but also improving device performance
Electronic Nanodevices
The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications
Tunnel Field Effect Transistors:from Steep-Slope Electronic Switches to Energy Efficient Logic Applications
The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteristics. The main differences of a Tunnel FET with respect to a conventional MOSFET is pointed out and the differences have been explained. A compact DC/AC model has been developed which is capable of describing the I-V characteristics in all regimes of operation. The model takes in to account ambi-polarity, drain side breakdown and all tunneling related physics. A temperature dependence is also added to the model to study the temperature independent behavior of tunneling. The model was further implemented in a Verilog-A based circuit simulator. Following calibration to experimental results of Silicon and strained-Silicon TFETs, the model has been also used to benchmark against a standard CMOS node for digital and analog applications. The circuits built with Tunnel FETs showed interesting temperature behavior which was superior to the compared CMOS node. In the same work, we also explore and propose solutions for using TFETs for low power memory applications. Both volatile and non-volatile memory concepts are investigated and explored. The application of a Tunnel FET as a capacitor-less memory has been experimentally demonstrated for the first time. New device concepts have been proposed and process flows for the same are developed to realize them in the clean room in EPFL
Advances in Solid State Circuit Technologies
This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields
๋์ ์ ๋ฅ ๊ตฌ๋๋ฅ๋ ฅ์ ๊ฐ์ง๋ SiGe ๋๋ ธ์ํธ ๊ตฌ์กฐ์ ํฐ๋๋ง ์ ๊ณํจ๊ณผ ํธ๋์ง์คํฐ
ํ์๋
ผ๋ฌธ (๋ฐ์ฌ) -- ์์ธ๋ํ๊ต ๋ํ์ : ๊ณต๊ณผ๋ํ ์ ๊ธฐยท์ ๋ณด๊ณตํ๋ถ, 2021. 2. ๋ฐ๋ณ๊ตญ.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET.
In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.์ด๊ณ ๋ฐ๋ ์ง์ ํ๋ก ๊ธฐ์ ์ ๋ฐ์ ์ ๊ณ ์ง์ ๋ ๋ฌ์ฑ์ ํตํด ๋จ์ ์นฉ์ ์ฐ์ฐ ์๋ ๋ฐ ์ฉ๋ ํฅ์์ ๊ธฐ์ฌํ ์ํ์ ์์๋ฅผ ๋์์์ด ์๊ตฌํ๊ณ ์๋ค. ํ์ง๋ง ์ต์ ์ ์๋ณดํ ๊ธ์-์ฐํ๋ง-๋ฐ๋์ฒด (CMOS) ๊ธฐ์ ์์ ๊ธ์-์ฐํ๋ง-๋ฐ๋์ฒด ์ ๊ณ ํจ๊ณผ ํธ๋์ง์คํฐ (MOSFET) ์ ๋จ์ํ ์ํํ๋ ๋ ์ด์ ์ง์ ํ๋ก์ ์ฑ๋ฅ ํฅ์์ ๋ณด์ฅํด ์ฃผ์ง ๋ชปํ๊ณ ์๋ค. ํนํ ์์์ ํฌ๊ธฐ๊ฐ ์ค์ด๋๋ ๋ฐ๋ฉด ์ ์ ์ ๋ ฅ ์๋ชจ๋์ ์ ์ ์ค์ผ์ผ๋ง์ ๋ํ๋ก ์ธํด ๊ฐ์๋์ง ์๊ณ ์๋ ์ํฉ์ด๋ค. MOSFET์ ์งง์ ์ฑ๋ ํจ๊ณผ๋ก ์ธํด ์ฆ๊ฐ๋ ๋์ค ์ ๋ฅ๊ฐ ์ ์ ์ค์ผ์ผ๋ง์ ์ด๋ ค์์ ์ฃผ๋ ๋ํ์ ์์ธ์ผ๋ก ๊ผฝํ๋ค. ์ด๋ฌํ ๊ทผ๋ณธ์ ์ธ MOSFET์ ํ๊ณ๋ฅผ ๊ทน๋ณตํ๊ธฐ ์ํ์ฌ ์ง๋ 10์ฌ๋
๊ฐ ์๋ก์ด ๋จ๊ณ์ ์ ๊ณ ํจ๊ณผ ํธ๋์ง์คํฐ ์์๋ค์ด ์ฐ๊ตฌ๋๊ณ ์๋ค. ๊ทธ ์ค ํฐ๋ ์ ๊ณ ํจ๊ณผ ํธ๋์ง์คํฐ(TFET)์ ๊ทธ ํน์ ์ ์ฐ์ํ ์ ์ ํน์ฑ์ผ๋ก ๊ฐ๊ด๋ฐ์ ์ง์ค์ ์ผ๋ก ์ฐ๊ตฌ๋๊ณ ์๋ค. ๋ง์ ์ฐ๊ตฌ์๋ ๋ถ๊ตฌํ๊ณ , TFET์ ๋ถ์กฑํ ์ ๋ฅ ๊ตฌ๋ ๋ฅ๋ ฅ์ MOSFET์ ๋์ฒด์ฌ๋ก ์๋ฆฌ๋งค๊นํ๋ ๋ฐ ๊ฐ์ฅ ํฐ ๋ฌธ์ ์ ์ด ๋๊ณ ์๋ค.
๋ณธ ํ์๋
ผ๋ฌธ์์๋ ์๊ธฐ๋ ๋ฌธ์ ์ ์ ํด๊ฒฐํ ์ ์๋ ์ฐ์ํ ์ ๋ฅ ๊ตฌ๋ ๋ฅ๋ ฅ์ ๊ฐ์ง TFET์ด ์ ์๋์๋ค. ๋ฐ์ก์ ์ ์
๊ณผ ๊ฒ์ดํธ ์ปจํธ๋กค์ ํฅ์์ํฌ ์ ์๋ ์์ง ์ ์ธต๋ ์ค๋ฆฌ์ฝ์ ๋ง๋(SiGe) ๋๋
ธ์ํธ ์ฑ๋์ด ์ฌ์ฉ๋์๋ค. ๋ํ, ์ ์๋ TFET์ CMOS ๊ธฐ๋ฐ ๊ณต์ ์ ํ์ฉํ์ฌ MOSFET๊ณผ ํจ๊ป ์ ์๋์๋ค. ํ
ํฌ๋๋ก์ง ์ปดํจํฐ ์ง์ ์ค๊ณ(TCAD) ์๋ฎฌ๋ ์ด์
๊ณผ ์ค์ ์ธก์ ๊ฒฐ๊ณผ๋ฅผ ํ์ฉํ์ฌ ์ ์๋ ์์์ ์ฐ์์ฑ์ ๊ฒ์ฆํ์๋ค. ๋จ์ CMOS ์์์ ๊ด์ ์์, ์ ์ ํน์ฑ๊ณผ ์ ๋ฅ ๊ตฌ๋ ๋ฅ๋ ฅ์ ํฅ์์ ์ ๋์ , ์ ์ฑ์ ๋ฐฉ๋ฒ์ผ๋ก ๋ถ์ํ์๋ค. ๊ทธ๋ฆฌ๊ณ , ์ ์๋ ์์์ ์ฑ๋ฅ์ ๊ธฐ์กด ์ ์ ๋ฐ ๋ณด๊ณ ๋ TFET ๋ฐ ํจ๊ป ์ ์๋ MOSSFET๊ณผ ๋น๊ตํ์๋ค. ์ด๋ฌํ ๊ณผ์ ์ ํตํด, ์ค๋ฆฌ์ฝ์ ๋ง๋ ๋๋
ธ์ํธ TFET์ ํ์ฉ ๊ฐ๋ฅ์ฑ์ด ์
์ฆ๋์๋ค. ์ ์๋ ์ค๋ฆฌ์ฝ์ ๋ง๋ ๋๋
ธ์ํธ ์์๋ ์ฃผ๋ชฉํ ๋งํ ์ ์ ํน์ฑ์ ๊ฐ์ก๊ณ ์ ์ ์ ๊ตฌ๋ ํ๊ฒฝ์์ ํ์ธต ๋ ๋ฎ์ ๋์ค ์ ๋ฅ๋ฅผ ๊ฐ์ง์ผ๋ก์จ ํฅํ MOSFET์ ๋์ฒดํ ๋งํ ์ถฉ๋ถํ ๊ฐ๋ฅ์ฑ์ ๋ณด์ฌ์ฃผ์๋ค.Chapter 1 Introduction 1
1.1. Power Crisis of Conventional CMOS Technology 1
1.2. Tunnel Field-Effect Transistor (TFET) 6
1.3. Feasibility and Challenges of TFET 9
1.4. Scope of Thesis 11
Chapter 2 Device Characterization 13
2.1. SiGe Nanosheet TFET 13
2.2. Device Concept 15
2.3. Calibration Procedure for TCAD simulation 17
2.4. Device Verification with TCAD simulation 21
Chapter 3 Device Fabrication 31
3.1. Fabrication Process Flow 31
3.2. Key Processes for SiGe Nanosheet TFET 33
3.2.1. Key Process 1 : SiGe Nanosheet Formation 34
3.2.2. Key Process 2 : Source/Drain Implantation 41
3.2.3. Key Process 3 : High-ฮบ/Metal gate Formation 43
Chapter 4 Results and Discussion 53
4.1. Measurement Results 53
4.2. Analysis of Device Characteristics 56
4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56
4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62
4.3. Performance Evaluation through Benchmarks 64
4.4. Optimization Plan for SiGe nanosheet TFET 66
4.4.1. Improvement of Quality of Gate Dielectric 66
4.4.2. Optimization of Doping Junction at Source 67
Chapter 5 Conclusion 71
Bibliography 73
Abstract in Korean 81
List of Publications 83Docto
Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits
Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based
designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moorรขโฌโขs Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable
by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility.
The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that
exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower
applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve
the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference
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