Effect of the output impedance in multiphase active clamp buck converters

Passive current sharing in multiphase converters, where resistive losses are not dominant, is a quite complex goal. In this paper, an averaged model of an active clamp buck converter was obtained. It has been checked that this topology presents high output impedance. This property is used like a lossless passive equalization. The principle of operation, theoretical analysis, simulation, and experimental results are presented, taken from a three-stage laboratory prototype.This work was supported by the Ministry of Education and Science, Spain, under Research Project COMPAS (Code DPI2007-64135)

Effect of the output impedance of active clamp topology in multiphase converters

Passive current sharing in multiphase converters, where resistive losses are not dominant, is a quite complex goal. In this paper an averaged model of an active clamp converter was obtained. It has been checked that these topologies present high output impedance. This property is used like a lossless passive equalization. Simulated results of the average model accuracy and current sharing are presented

Chemical And Biological Treatment Of Mature Landfill Leachate

The challenges imposed on Voltage Regulator Modules (VRM) become difficult to be achieved with the conventional multiphase buck converter commonly used on PC motherboards. For faster data transfer, a decrease in the output voltage is needed. This decrease causes small duty cycle that is accompanied by critical problems which impairs the efficiency. Therefore, these problems need to be addressed. Transformer-based non-isolated topologies are not new approaches to extend the duty cycle and avoid the associated drawbacks. High leakage, several added components and complicated driving and control schemes are some of the trade-offs to expand the duty cycle. The objective of this work is to present a new dc-dc buck-based topology, which extends the duty cycle with minimum drawbacks by adding two transformers that can be integrated to decrease the size and two switches with zero voltage switching (ZVS). Another issue addressed in this thesis is deriving a small signal model for a two-input two-phase buck converter as an introduction to a new evolving field of multi-input converters

Local control of multiple module converters with ratings-based load sharing

Multiple module dc-dc converters show promise in meeting the increasing demands on ef- ficiency and performance of energy conversion systems. In order to increase reliability, maintainability, and expandability, a modular approach in converter design is often desired. This thesis proposes local control of multiple module converters as an alternative to using a central controller or master controller. A power ratings-based load sharing scheme that allows for uniform and non-uniform sharing is introduced. Focus is given to an input series, output parallel (ISOP) configuration and modules with a push-pull topology. Sensorless current mode (SCM) control is digitally implemented on separate controllers for each of the modules. The benefits of interleaving the switching signals of the distributed modules is presented. Simulation and experimental results demonstrate stable, ratings-based sharing in an ISOP converter with a high conversion ratio for both uniform and non-uniform load sharing cases

Multiphase current-controlled buck converter with energy recycling output impedance correction circuit (OICC)

This study is related to the improvement of the output impedance of a multiphase buck converter with peak current mode control (PCMC) by means of introducing an additional power path, which virtually increases the output capacitance during transients. Various solutions that can be employed to improve the dynamic behavior of the converter system exist, but nearly all solutions are developed for a single-phase buck converter with voltage mode control, while in the voltage regulation module applications, due to the high currents and dynamic specifications, the system is usually implemented as a multiphase buck converter with current mode control to ensure current sharing. The proposed circuit, output impedance correction circuit (OICC), is used to inject or extract a current n - 1 times larger than the output capacitor current, thus virtually increasing n times the value of the output capacitance during the transients. Furthermore, the OICC concept is extended to a multiphase buck converter system and the proposed solution is compared with the system that has n times bigger output capacitor in terms of dynamic behavior and static and dynamic efficiency. The OICC is implemented as a synchronous buck converter with PCMC, thus reducing its penalty on the system efficiency

Transient Response Improvement For Multi-phase Voltage Regulators

Next generation microprocessor (Vcore) requirements for high current slew rates and fast transient response together with low output voltage have posed great challenges on voltage regulator (VR) design . Since the debut of Intel 80X86 series, CPUs have greatly improved in performance with a dramatic increase on power consumption. According to the latest Intel VR11 design guidelines , the operational current may ramp up to 140A with typical voltages in the 1.1V to 1.4V range, while the slew rate of the transient current can be as high as 1.9A/ns [1, 2]. Meanwhile, the transient-response requirements are becoming stringer and stringer. This dissertation presents several topics on how to improve transient response for multi-phase voltage regulators. The Adaptive Modulation Control (AMC) is a type of non-linear control method which has proven to be effective in achieving high bandwidth designs as well as stabilizing the control loop during large load transients. It adaptively adjusts control bandwidth by changing the modulation gain, depending on different load conditions. With the AMC, a multiphase voltage regulator can be designed with an aggressively high bandwidth. When in heavy load transients where the loop could be potentially unstable, the bandwidth is lowered. Therefore, the AMC provides an optimal means for robust high-bandwidth design with excellent transient performance. The Error Amplifier Voltage Positioning (EAVP) is proposed to improve transient response by removing undesired spikes and dips after initial transient response. The EAVP works only in a short period of time during transient events without modifying the power stage and changing the control loop gain. It facilitates the error amplifier voltage recovering during transient events, achieving a fast settling time without impact on the whole control loop. Coupled inductors are an emerging topology for computing power supplies as VRs with coupled inductors show dynamic and steady-state advantages over traditional VRs. This dissertation first covers the coupling mechanism in terms of both electrical and reluctance modeling. Since the magnetizing inductance plays an important role in the coupled-inductor operation, a unified State-Space Averaging model is then built for a two-phase coupled-inductor voltage regulator. The DC solutions of the phase currents are derived in order to show the impact of the magnetizing inductance on phase current balancing. A small signal model is obtained based on the state-space-averaging model. The effects of magnetizing inductance on dynamic performance are presented. The limitations of conventional DCR current-sensing for coupled inductors are addressed. Traditional inductor DCR current sensing topology and prior arts fail to extract phase currents for coupled inductors. Two new DCR current sensing topologies for coupled inductors are presented in this dissertation. By implementation of simple RC networks, the proposed topologies can preserve the coupling effect between phases. As a result, accurate phase inductor currents and total current can be sensed, resulting in excellent current and voltage regulation. While coupled-inductor topologies are showing advantages in transient response and are becoming industry practices, they are suffering from low steady-state operating efficiency. Motivated by the challenging transient and efficiency requirements, this dissertation proposes a Full Bridge Coupled Inductor (FBCI) scheme which is able to improve transient response as well as savor high efficiency at (a) steady state. The FBCI can change the circuit configuration under different operational conditions. Its flexible topology is able to optimize both transient response and steady-state efficiency. The flexible core configuration makes implementation easy and clear of IP issues. A novel design methodology for planar magnetics based on numerical analysis of electromagnetic fields is offered and successfully applied to the design of low-voltage high power density dc-dc converters. The design methodology features intense use of FEM simulation. The design issues of planar magnetics, including loss mechanism in copper and core, winding design on PCB, core selections, winding arrangements and so on are first reviewed. After that, FEM simulators are introduced to numerically compute the core loss and winding loss. Consequently, a software platform for magnetics design is established, and optimized magnetics can then be achieved. Dynamic voltage scaling (DVS) technology is a common industry practice in optimizing power consumption of microprocessors by dynamically altering the supply voltage under different operational modes, while maintaining the performance requirements. During DVS operation, it is desirable to position the output voltage to a new level commanded by the microprocessor (CPU) with minimum delay. However, voltage deviation and slow settling time usually exist due to large output capacitance and compensation delay in voltage regulators. Although optimal DVS can be achieved by modifying the output capacitance and compensation, this method is limited by constraints from stringent static and dynamic requirements. In this dissertation, the effects of output capacitance and compensation network on DVS operation are discussed in detail. An active compensator scheme is then proposed to ensure smooth transition of the output voltage without change of power stage and compensation during DVS. Simulation and experimental results are included to demonstrate the effectiveness of the proposed scheme

Integrated design of high performance pulsed power converters : application to klystron modulators for the compact linear colider (CLIC)

Ce travail de recherche présente l’étude, conception et validation d’une topologie de convertisseur de puissance pulsé qui compense la chute de tension pour des modulateurs de type klystron de haute performance. Cette topologie est capable de compenser la chute de tension du banc de condensateur principal et, en même temps, de faire fonctionner le modulateur avec une consommation de puissance constante par rapport au réseau électrique. Ces spécifications sont requises par le projet Compact Linear Collider (CLIC) pour les modulateurs klystron de son Drive Beam. Le dimensionnement du système est effectué à partir d’un outil d’optimisation globale développé à partir des modèles analytiques qui décrivent les performances de chaque composant du système. Tous les modèles sont intégrés dans un processus optimal intermédiaire de conception qui utilise des techniques d’optimisation afin de réaliser un dimensionnement optimal du système. Les performances de cette solution optimale intermédiaire sont alors évaluées à l’aide d’un modèle plus fin basé sur des simulations numériques. Une technique d’optimisation utilisant l’approche «space mapping» est alors mise en oeuvre. Si l’écart entre les performances prédites et les performances simulées est important, des facteurs de correction sont appliqués aux modèles analytiques et le processus d’optimisation est relancé. Cette méthode permet d’obtenir une solution optimale validée par le modèle fin en réduisant le nombre de simulations. La topologie finale sélectionnée pour le cahier des charges du modulateur CLIC est validée expérimentalement sur des prototypes à échelle réduite. Les résultats valident la méthodologie de dimensionnement et respectent les spécifications.This research work presents the study, design and validation of a pulsed power converter topology that performs accurate voltage droop compensation for high performance klystron modulators. This topology is capable of compensating the voltage droop of the intermediate capacitor bank and, at the same time, it makes possible a constant power consumption operation of the modulator from the utility grid. These two main specifications are required for the Compact Linear Collider (CLIC) Drive Beam klystron modulators. The dimensioning of the system is performed by developing a global optimization design tool. This tool is first based on developed analytical models describing the performances of each system subcomponent. All these models are integrated into an intermediate design environment that uses nonlinear optimization techniques to calculate an optimal dimensioning of the system. The intermediate optimal solution performances are then evaluated using a more accurate model based on numerical simulation. Therefore, an optimization technique using «space mapping» is implemented. If differences between predicted performances and simulated results are non-negligible, correction factors are applied to the analytical models and the optimization process is launched again. This method makes possible to achieve an optimal solution validated by numerical simulation while reducing the number of numerical simulation steps. The selected final topology for the CLIC klystron modulator is experimentally validated using reduced scale prototypes. Results validate the selected methodology and fulfill the specifications

Survey on Photo-Voltaic Powered Interleaved Converter System

Renewable energy is the best solution to meet the growing demand for energy in the country. The solar energy is considered as the most promising energy by the researchers due to its abundant availability, eco-friendly nature, long lasting nature, wide range of application and above all it is a maintenance free system. The energy absorbed by the earth can satisfy 15000 times of today’s total energy demand and its hundred times more than that our conventional energy like coal and other fossil fuels. Though, there are overwhelming advantages in solar energy, It has few drawbacks as well such as its low conversion ratio, inconsistent supply of energy due to variation in the sun light, less efficiency due to ripples in the converter, time dependent and, above all, high capitation cost. These aforementioned flaws have been addressed by the researchers in order to extract maximum energy and attain hundred percentage benefits of this heavenly resource. So, this chapter presents a comprehensive investigation based on photo voltaic (PV) system requirements with the following constraints such as system efficiency, system gain, dynamic response, switching losses are investigated. The overview exhibits and identifies the requirements of a best PV power generation system

Development of Improved Performance Switchmode Converters for Critical Load Applications

Emerging portable applications and the rapid advancement of technology have posed rigorous challenges to power engineers for an efficient power delivery at high power density. The foremost objectives are to develop high efficiency, high power density topologies such as: buck, synchronous buck and multiphase buck converters, with the implementation of soft switching technology to reduce switching losses maintaining voltage and current stresses within the permissible range. Demand of low voltage power supply for telecom system leads to narrow duty cycle which compels to increase operating switching frequency. Design of conventional buck converter under narrow duty cycle is quite objectionable since it leads to poor utilization of components as well as it degrades the system efficiency. A high switching frequency operation reduces the switch conduction time that leads to large increase in switching losses and increases the control complexity. Therefore, duty cycle has to be extended and at the same time switching losses have to be minimized. Transformer based topology can be used to extend the duty cycle. But to reduce switching losses soft switching techniques should be implemented. An isolated buck converter with simple clamp capacitor scheme is proposed to reduce switching losses and to extend duty cycle by optimizing the turn ratio. Extended duty cycle impose limit on dead time. Dead time has to be controlled with respect to duty cycle to reduce body diode conduction loss and to avoid the shoot through conditions in our proposed topology. The proposed clamp capacitor scheme control the dead time as well as provide better efficiency with reduction in switching losses maintaining ripples within the allowable range