5,743 research outputs found
An analog building block for signal conditioning instrumentation circuits
The design of analog signal conditioning circuits for instrumentation applications often requires designing a specific circuit for each case. For board-level design solutions, these circuits are generally implemented by using Operational Amplifiers (OA) and Instrumentation Amplifiers (IA). An analog building block (ABB) is proposed, which can be implemented with three standard OAs. Using different connection schemes and just adding a few resistors, it allows implementing several analog circuits such as common-mode conditioners, single-ended to differential and differential to single-ended converters, voltage and current amplifiers, current-to-voltage and voltage-to-current converters, among others. The proposed ABB is analyzed and applied to several typical analog conditioning problems. The design equations and experimental results for these circuits are presented.Fil: Spinelli, Enrique Mario. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; ArgentinaFil: Haberman, Marcelo Alejandro. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales. Universidad Nacional de La Plata. Instituto de Investigaciones en Electrónica, Control y Procesamiento de Señales; Argentin
Study of Adjustable Gains for Control of Oscillation Frequency and Oscillation Condition in 3R-2C Oscillator
An idea of adjustable gain in order to obtain controllable features is very useful for design of tuneable oscillators. Several active elements with adjustable properties (current and voltage gain) are discussed in this paper. Three modified oscillator conceptions that are quite simple, directly electronically adjustable, providing independent control of oscillation condition and frequency were designed. Positive and negative aspects of presented method of control are discussed. Expected assumptions of adjustability are verified experimentally on one of the presented solution
A design method for active high-CMRR fully-differential circuits
Postprint (published version
Novel active function blocks and their applications in frequency filters and quadrature oscillators
Kmitočtové filtry a sinusoidní oscilátory jsou lineární elektronické obvody, které jsou používány v široké oblasti elektroniky a jsou základními stavebními bloky v analogovém zpracování signálu. V poslední dekádě pro tento účel bylo prezentováno velké množství stavebních funkčních bloků. V letech 2000 a 2006 na Ústavu telekomunikací, VUT v Brně byly definovány univerzální proudový konvejor (UCC) a univerzální napět'ový konvejor (UVC) a vyrobeny ve spolupráci s firmou AMI Semiconductor Czech, Ltd. Ovšem, stále existuje požadavek na vývoj nových aktivních prvků, které nabízejí nové výhody. Hlavní přínos práce proto spočívá v definici dalších původních aktivních stavebních bloků jako jsou differential-input buffered and transconductance amplifier (DBTA), current follower transconductance amplifier (CFTA), z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), generalized current follower differential input transconductance amplifier (GCFDITA), voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), a minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Pomocí navržených aktivních stavebních bloků byly prezentovány původní zapojení fázovacích článků prvního řádu, univerzální filtry druhého řádu, ekvivalenty obvodu typu KHN, inverzní filtry, aktivní simulátory uzemněného induktoru a kvadraturní sinusoidní oscilátory pracující v proudovém, napět'ovém a smíšeném módu. Chování navržených obvodů byla ověřena simulací v prostředí SPICE a ve vybraných případech experimentálním měřením.Frequency filters and sinusoidal oscillators are linear electric circuits that are used in wide area of electronics and also are the basic building blocks in analogue signal processing. In the last decade, huge number of active building blocks (ABBs) were presented for this purpose. In 2000 and 2006, the universal current conveyor (UCC) and the universal voltage conveyor (UVC), respectively, were designed at the Department of Telecommunication, BUT, Brno, and produced in cooperation with AMI Semiconductor Czech, Ltd. There is still the need to develop new active elements that offer new advantages. The main contribution of this thesis is, therefore, the definition of other novel ABBs such as the differential-input buffered and transconductance amplifier (DBTA), the current follower transconductance amplifier (CFTA), the z-copy current-controlled current inverting transconductance amplifier (ZC-CCCITA), the generalized current follower differential input transconductance amplifier (GCFDITA), the voltage gain-controlled modified current-feedback operational amplifier (VGC-MCFOA), and the minus-type current-controlled third-generation voltage conveyor (CC-VCIII-). Using the proposed ABBs, novel structures of first-order all-pass filters, second-order universal filters, KHN-equivalent circuits, inverse filters, active grounded inductance simulators, and quadrature sinusoidal oscillators working in the current-, voltage-, or mixed-mode are presented. The behavior of the proposed circuits has been verified by SPICE simulations and in selected cases also by experimental measurements.
Low Voltage Low Power Analogue Circuits Design
Disertační práce je zaměřena na výzkum nejběžnějších metod, které se využívají při návrhu analogových obvodů s využití nízkonapěťových (LV) a nízkopříkonových (LP) struktur. Tyto LV LP obvody mohou být vytvořeny díky vyspělým technologiím nebo také využitím pokročilých technik návrhu. Disertační práce se zabývá právě pokročilými technikami návrhu, především pak nekonvenčními. Mezi tyto techniky patří využití prvků s řízeným substrátem (bulk-driven - BD), s plovoucím hradlem (floating-gate - FG), s kvazi plovoucím hradlem (quasi-floating-gate - QFG), s řízeným substrátem s plovoucím hradlem (bulk-driven floating-gate - BD-FG) a s řízeným substrátem s kvazi plovoucím hradlem (quasi-floating-gate - BD-QFG). Práce je také orientována na možné způsoby implementace známých a moderních aktivních prvků pracujících v napěťovém, proudovém nebo mix-módu. Mezi tyto prvky lze začlenit zesilovače typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za účelem potvrzení funkčnosti a chování výše zmíněných struktur a prvků byly vytvořeny příklady aplikací, které simulují usměrňovací a induktanční vlastnosti diody, dále pak filtry dolní propusti, pásmové propusti a také univerzální filtry. Všechny aktivní prvky a příklady aplikací byly ověřeny pomocí PSpice simulací s využitím parametrů technologie 0,18 m TSMC CMOS. Pro ilustraci přesného a účinného chování struktur je v disertační práci zahrnuto velké množství simulačních výsledků.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the non–conventional ones which are bulk–driven (BD), floating–gate (FG), quasi–floating–gate (QFG), bulk–driven floating–gate (BD–FG) and bulk–driven quasi–floating–gate (BD–QFG) techniques. The thesis also looks at ways of implementing structures of well–known and modern active elements operating in voltage–, current–, and mixed–mode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fully–differential second generation current conveyor (FB–CCII), fully–balanced differential difference amplifier (FB–DDA), voltage differencing transconductance amplifier (VDTA), current–controlled current differencing buffered amplifier (CC–CDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diode–less rectifier and inductance simulations, as well as low–pass, band–pass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
The design of active resistors and transductors in a CMOS technology
Merged with duplicate record 10026.1/2618 on 07.20.2017 by CS (TIS)This thesis surveys linearisation techniques for implementing monolithic MOS
active resistors and transconductors, and investigates the design of linear tunable
resistors and transconductors. Improving linearity and tunability in the presence
of non-ideal factors such as bulk modulation, mobility-degradation effects and mismatch
of transistors is a principal objective. A family of new non-saturation-mode
resistors and two novel saturation-mode transconductors are developed. Where
possible, approximate analytical expressions are derived to explain the principles
of operation. Performance comparisons of the new structures are made with other
well-known circuits and their relative advantages and disadvantages evaluated.
Experimental and simulation results are presented which validate the proposed
linearisation techniques. It is shown that the proposed family of resistors offers
improved linearity whilst the transconductors combine extended tunability with
low distortion. Continuous-time filter examples are given to demonstrate the
potential of these circuits for application in analogue signal-processing tasks.GEC Plessey Semiconductors, Plymout
A 0.3 V, rail-to-rail, ultralow-power, non-tailed, body-driven, sub-threshold amplifier
A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is
proposed in this paper. The input stage exploits a replica bias control loop to set the common mode
current and a common mode feed-forward strategy to set its output common mode voltage. This
novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered
operational amplifier. A dual path compensation strategy is exploited to improve the frequency
response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology
from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power
consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around
3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of
60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state
of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and
Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and
mismatch variations
Design of a Comparator and an Amplifier in CMOS using standard logic gates
Using standard logic gates in CMOS, or standard-cells, has the advantage of full synthe-
sizability, as well as the voltage scalability between technologies. In this work a general pur-
pose standard-cell-based voltage comparator and amplifier are presented.
The objective is to design a general purpose standard-cell-based comparator and ampli-
fier in 130 nm CMOS by optimizing the already existing topologies with the aim of improving
some of the specifications of the studied topologies.
Various simulation testbenches were made to test the studied topologies of comparators
and amplifiers, in which the results were compared. The top performing standard-cell com-
parator and amplifier were then modified. After successfully designing the comparator, it was
used in the design of an opamp-less Sigma-Delta modulator (ΣΔM).
The proposed comparator is an OR-AND-Inverter-based comparator with dual inputs
and outputs, achieving a delay of 109 ps, static input offset of 591 μV, and random offset of
10.42 μV, while dissipating 890 μW, when clocked at 1.5 GHz.
The proposed amplifier is a single-path three-stage inverter-based operational transcon-
ductance amplifier (OTA) with active common-mode feedback loop, achieving a DC gain of
63 dB, 1444 MHz of unity-gain bandwidth, 51º of phase margin while dissipating 1098 μW,
considering a load of 1 pF.
The proposed comparator was employed in the ΣΔM with a standard-cell based edge-
triggered flip-flop. The ΣΔM, with a sampling frequency of 2 MHz and a signal bandwidth of
2.5 kHz, achieved a peak SNDR of 69 dB while dissipating only 136.7 μW.Utilizando portas lógicas básicas em CMOS oferece a vantagem de um circuito comple-
tamente sintetizável, tal como o escalamento de tensão entre tecnologias. Neste trabalho são
apresentados um comparador de tensão e um amplificador utilizando portas lógicas.
O objetivo deste trabalho é desenhar um comparador e um amplificador utilizando por-
tas lógicas através do estudo e otimização de topologias já existentes com a finalidade de me-
lhoramento de algumas das especificações das mesmas.
Foram realizados vários bancos de teste para testar as topologias estudadas de compa-
radores e amplificadores, em que os resultados foram comparados. As topologias de compa-
radores e amplificadores de portas lógicas com melhor performance foram então modificadas.
Após o comparador ter sido projetado com sucesso, foi utilizado na projeção de um modula-
dor
Sigma-Delta (ΣΔM)
opamp-less.
O comparador proposto é um
OR-AND-Inversor com duas entradas e saídas, que apre-
senta um atraso de 109 ps,
offset estático na entrada de 591 μV,
offset aleatório de 10.42 μV,
enquanto dissipando 890 μW, utilizando uma frequência de relógio de 1.5 GHz
O amplificador proposto é um amplificador operacional de transcondutância
single-
path three-stage inverter-based com um
loop ativo de realimentação do modo-comum, que
apresenta um ganho DC de 63 dB, 1444 MHz de ganho-unitário de largura de banda, 51º de
margem de fase e dissipando 1098 μW, considerando uma carga de 1 pF.
O comparador proposto foi aplicado no ΣΔM com um
flip-flop edge-triggered baseado
em portas lógicas. O ΣΔM, com uma frequência de amostragem de 2 MHz e uma largura de
banda de 2.5 kHz, apresentou um SNDR máximo de 69 dB enquanto dissipando apenas 136.7
μW
The Measurement of AM noise of Oscillators
The close-in AM noise is often neglected, under the assumption that it is a
minor problem as compared to phase noise. With the progress of technology and
of experimental science, this assumption is no longer true. Yet, information in
the literature is scarce or absent. This report describes the measurement of
the AM noise of rf/microwave sources in terms of Salpha(f), i.e., the power
spectrum density of the fractional amplitude fluctuation alpha. The proposed
schemes make use of commercial power detectors based on Schottky and tunnel
diodes, in single-channel and correlation configuration. There follow the
analysis of the front-end amplifier at the detector output, the analysis of the
methods for the measurement of the power-detector noise, and a digression about
the calibration procedures. The measurement methods are extended to the
relative intensity noise (RIN) of optical beams, and to the AM noise of the
rf/microwave modulation in photonic systems. Some rf/microwave synthesizers and
oscillators have been measured, using correlation and moderate averaging. As an
example, the flicker noise of a low-noise quartz oscillator (Wenzel 501-04623E)
is Salpha = 1.15E-13/f, which is equivalent to an Allan deviation of
sigma_alpha = 4E-7. The measurement systems described exhibit the world-record
lowest background noise.Comment: 39 pages, 22 figures, 8 tables, 21 references, list of symbol
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