A novel, inverter-based, fully differential, body-driven, rail-to-rail, input stage topology is
proposed in this paper. The input stage exploits a replica bias control loop to set the common mode
current and a common mode feed-forward strategy to set its output common mode voltage. This
novel cell is used to build an ultralow voltage (ULV), ultralow-power (ULP), two-stage, unbuffered
operational amplifier. A dual path compensation strategy is exploited to improve the frequency
response of the circuit. The amplifier has been designed in a commercial 130 nm CMOS technology
from STMicroelectronics and is able to operate with a nominal supply voltage of 0.3 V and a power
consumption as low as 11.4 nW, while showing about 65 dB gain, a gain bandwidth product around
3.6 kHz with a 50 pF load capacitance and a common mode rejection ratio (CMRR) in excess of
60 dB. Transistor-level simulations show that the proposed circuit outperforms most of the state
of the art amplifiers in terms of the main figures of merit. The results of extensive parametric and
Monte Carlo simulations have demonstrated the robustness of the proposed circuit to PVT and
mismatch variations