68 research outputs found
Benchmarking the screen-grid field effect transistor (SGrFET) for digital applications
Continuous scaling of CMOS technology has now reached a state of evolution, therefore,
novel device structures and new materials have been proposed for this purpose. The Screen-
Grid field Effect Transistor is introduced as a as a novel device structure that takes advantage
of several innovative aspects of the FinFET while introducing new geometrical feature to
improve a FET device performance. The idea is to design a FET which is as small as possible
without down-scaling issues, at the same time satisfying optimum device performance for
both analogue and digital applications. The analogue operation of the SGrFET shows some
promising results which make it interesting to continue the investigation on SGrFET for
digital applications. The SGrFET addresses some of the concerns of scaled CMOS such as
Drain Induce Barrier Lowering and sub-threshold slope, by offering the superior short
channel control. In this work in order to evaluate SGrFET performance, the proposed device
compared to the classical MOSFET and provides comprehensive benchmarking with
finFETs. Both AC and DC simulations are presented using TaurusTM and MediciTM
simulators which are commercially available via Synopsis. Initial investigation on the novel
device with the single gate structure is carried out. The multi-geometrical characteristic of the
proposed device is used to reduce parasitic capacitance and increase ION/IOFF ratio to improve
device performance in terms of switching characteristic in different circuit structures. Using
TaurusTM AC simulation, a small signal circuit is introduced for SGrFET and evaluated using
both extracted small signal elements from TaurusTM and Y-parameter extraction.
The SGrFET allows for the unique behavioural characteristics of an independent-gate device.
Different configurations of double-gate device are introduced and benchmark against the
finFET serving as a double gate device. Five different logic circuits, the complementary and
N-inverter, the NOR, NAND and XOR, and controllable Current Mirror circuits are
simulated with finFET and SGrFET and their performance compared. Some digital key
merits are extracted for both finFET and SGrFET such as power dissipation, noise margin
and switching speed to compare the devices under the investigation performance against each
other. It is shown that using multi-geometrical feature in SGrFET together with its multi-gate
operation can greatly decrease the number of device needed for the logic function without
speed degradation and it can be used as a potential candidate in mix-circuit configuration as a
multi-gate device. The initial fabrication steps of the novel device explained together with
some in-house fabrication process using E-Beam lithography. The fabricated SGrFET is
characterised via electrical measurements and used in a circuit configuration
Characterisation of thermal and coupling effects in advanced silicon MOSFETs
PhD ThesisNew approaches to metal-oxide-semiconductor field effect transistor (MOSFET)
engineering emerge in order to keep up with the electronics market demands. Two main
candidates for the next few generations of Moore’s law are planar ultra-thin body and
buried oxide (UTBB) devices and three-dimensional FinFETs. Due to miniature
dimensions and new materials with low thermal conductivity, performance of advanced
MOSFETs is affected by self-heating and substrate effects. Self-heating results in an
increase of the device temperature which causes mobility reduction, compromised
reliability and signal delays. The substrate effect is a parasitic source and drain coupling
which leads to frequency-dependent analogue behaviour. Both effects manifest
themselves in the output conductance variation with frequency and impact analogue as
well as digital performance. In this thesis self-heating and substrate effects in FinFETs
and UTBB devices are characterised, discussed and compared. The results are used to
identify trade-offs in device performance, geometry and thermal properties. Methods
how to optimise the device geometry or biasing conditions in order to minimise the
parasitic effects are suggested.
To identify the most suitable technique for self-heating characterisation in advanced
semiconductor devices, different methods of thermal characterisation (time and
frequency domain) were experimentally compared and evaluated alongside an analytical
model. RF and two different pulsed I-V techniques were initially applied to partially
depleted silicon-on-insulator (PDSOI) devices. The pulsed I-V hot chuck method
showed good agreement with the RF technique in the PDSOI devices. However,
subsequent analysis demonstrated that for more advanced technologies the time domain
methods can underestimate self-heating. This is due to the reduction of the thermal time
constants into the nanosecond range and limitations of the pulsed I-V set-up. The
reduction is related to the major increase of the surface to volume ratio in advanced
MOSFETs. Consequently the work showed that the thermal properties of advanced
semiconductor devices must be characterised within the frequency domain.
For UTBB devices with 7-8 nm Si body and 10 nm ultra-thin buried oxide (BOX)
the analogue performance degradation caused by the substrate effects can be stronger
than the analogue performance degradation caused by self-heating. However, the
substrate effects can be effectively reduced if the substrate doping beneath the buried
ii
oxide is adjusted using a ground plane. In the MHz – GHz frequency range the intrinsic
voltage gain variation is reduced ~6 times when a device is biased in saturation if a
ground plane is implemented compared with a device without a ground plane.
UTBB devices with 25 nm BOX were compared with UTBB devices with 10 nm
BOX. It was found that the buried oxide thinning from 25 nm to 10 nm is not critical
from the thermal point of view as other heat evacuation paths (e.g. source and drain)
start to play a role.
Thermal and substrate effects in FinFETs were also analysed. It was experimentally
shown that FinFET thermal properties depend on the device geometry. The thermal
resistance of FinFETs strongly varies with the fin width and number of parallel fins,
whereas the fin spacing is less critical. The results suggest that there are trade-offs
between thermal properties and integration density, electrostatic control and design
complexity, since these aspects depend on device geometry. The high frequency
substrate effects were found to be effectively reduced in devices with sub-100 nm wide
fins.Engineering and Physical Sciences Research Council
(EPSRC) and EU fundin
Compact modeling of the rf and noise behavior of multiple-gate mosfets
La reducción de la tecnologÃa MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafÃos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analÃticos y compactos para cada una de las geometrÃas, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos
Caractérisation électrique et modélisation du transport dans matériaux et dispositifs SOI avancés
This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à -bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres
Modelling and simulation study of NMOS Si nanowire transistors
Nanowire transistors (NWTs) represent a potential alternative to Silicon FinFET technology in the 5nm CMOS technology generation and beyond. Their gate length can be scaled beyond the limitations of FinFET gate length scaling to maintain superior off-state leakage current and performance thanks to better electrostatic control through the semiconductor nanowire channels by gate-all-around (GAA) architecture. Furthermore, it is possible to stack nanowires to enhance the drive current per footprint. Based on these considerations, vertically-stacked lateral NWTs have been included in the latest edition of the International Technology Roadmap for Semiconductors (ITRS) to allow for further performance enhancement and gate pitch scaling, which are key criteria of merit for the new CMOS technology generation. However, electrostatic confinement and the transport behaviour in these devices are more complex, especially in or beyond the 5nm CMOS technology generation.
At the heart of this thesis is the model-based research of aggressively-scaled NWTs suitable for implementation in or beyond the 5nm CMOS technology generation, including their physical and operational limitations and intrinsic parameter fluctuations. The Ensemble Monte Carlo approach with Poisson-Schrödinger (PS) quantum corrections was adopted for the purpose of predictive performance evaluation of NWTs. The ratio of the major to the minor ellipsoidal cross-section axis (cross-sectional aspect ratio - AR) has been identified as a significant contributing factor in device performance. Until now, semiconductor industry players have carried out experimental research on NWTs with two different cross-sections: circular cylinder (or elliptical) NWTs and nanosheet (or nanoslab) NWTs. Each version has its own benefits and drawbacks; however, the key difference between these two versions is the cross-sectional AR. Several critical design questions, including the optimal NWT cross-sectional aspect ratio, remain unanswered. To answer these questions, the AR of a GAA NWT has been investigated in detail in this research maintaining the cross-sectional area constant. Signatures of isotropic charge distributions within Si NWTs were observed, exhibiting the same attributes as the golden ratio (Phi), the significance of which is well-known in the fields of art and architecture.
To address the gap in the existing literature, which largely explores NWT scaling using single-channel simulation, thorough simulations of multiple channels vertically-stacked NWTs have been carried out with different cross-sectional shapes and channel lengths. Contact resistance, non-equilibrium transport and quantum confinement effects have been taken into account during the simulations in order to realistically access performance and scalability.
Finally, the individual and combined effects of key statistical variability (SV) sources on threshold voltage (VT), subthreshold slope (SS), ON-current (Ion) and drain-induced barrier lowering (DIBL) have been simulated and discussed. The results indicate that the variability of NWTs is impacted by device architecture and dimensions, with a significant reduction in SV found in NWTs with optimal aspect ratios. Furthermore, a reduction in the variability of the threshold voltage has been observed in vertically-stacked NWTs due to the cancelling-out of variability in double and triple lateral channel NWTs
Miniaturized Transistors, Volume II
In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before
Strain-Engineered MOSFETs
This book brings together new developments in the area of strain-engineered MOSFETs using high-mibility substrates such as SIGe, strained-Si, germanium-on-insulator and III-V semiconductors into a single text which will cover the materials aspects, principles, and design of advanced devices, their fabrication and applications. The book presents a full TCAD methodology for strain-engineering in Si CMOS technology involving data flow from process simulation to systematic process variability simulation and generation of SPICE process compact models for manufacturing for yield optimization
Silicon on ferroelectric insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits
Title from PDF of title page, viewed on March 12, 2014Thesis advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 116-131)Thesis (M. S.)--School of Computer and Engineering. University of Missouri--Kansas City, 2013Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in subnanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based
designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor’s Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable
by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility.
The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that
exploits the concept of negative capacitance. The new field effect transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field Effect Transistor (SOF-FET). This proposal is a promising methodology for future ultra-lowpower
applications, because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers subthreshold swing significantly lower than 60mV/decade and reduced threshold voltage to form a conducting channel. The SOF-FET can also solve
the issue of junction leakage (due to the presence of unipolar junction between the top plate of the negative capacitance and the diffused areas that form the transistor source and drain). In this device the charge hungry ferroelectric film already limits the leakage.Abstract -- List of illustrations - List of tables -- Acknowledgements -- Dedication -- Introduction -- Carbon nanotube field effect transistor -- Multi-gate transistors -FinFET -- Subthreshold swing -- Tunneling field effect transistors -- I-mos and nanowire fets -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for soi-finfet -- Silicon-on-ferroelectric insulator field effect transistor (SOF-FET) -- Current-voltage characteristics of sof-fet -- Advantages, manufacturing process and future work of the proposed device -- Appendix -- Reference
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