Generalization of Linear Rosenstark Method of Feedback Amplifier Analysis to Nonlinear One

This paper deals with an extension of the Rosenstark’s linear model of an amplifier to a nonlinear one for the purpose of performing nonlinear distortion analysis. Contrary to an approach using phasors, our method uses the Volterra series. Relying upon the linear model mentioned above, we define first a set of the so-called amplifier’s constitutive equations in an operator form. Then, we expand operators using the Volterra series truncated to the first three components. This leads to getting two representations in the time domain, called in-network and inputoutput type descriptions of an amplifier. Afterwards, both of these representations are transferred into the multi-frequency domains. Their usefulness in calculations of any nonlinear distortion measure as, for example, harmonic, intermodulation, and/or cross-modulation distortion is demonstrated. Moreover, we show that they allow a simple calculation of the so-called nonlinear transfer functions in any topology as, for example, of cascade and feedback structures and their combinations occurring in single-, two-, and three-stage amplifiers. Examples of such calculations are given. Finally in this paper, we comment on usage of such notions as nonlinear signals, intermodulation nonlinearity, and on identification of transfer function poles and zeros lying on the frequency axis with related real-valued frequencies

Microwave Characteristics of an Independently Biased 3-stack InGaP/GaAs HBT Configuration

This paper investigates various important microwave characteristics of an independently biased 3-stack InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) chip at both small-signal and large-signal operation. By taking the advantage of the independently biased functionality, bias condition for individual transistor can be adjusted flexibly, resulting in the ability of independent control for both small-signal and large-signal performances. It was found that at small-signal operation stability and isolation characteristics of the proposed configuration can be significantly improved by controlling bias condition of the second-stage and the third-stage transistors while at large-signal operation its linearity and power gain can be improved through controlling the bias condition of the first-stage and the third-stage transistors. To demonstrate the benefits of using such an independently biased configuration, a measured optimum large-signal performance at an operation frequency of 1.6 GHz under an optimum bias condition for the high gain, low distortion were obtained as: PAE = 23.5 %, Pout = 12 dBm; Gain = 32.6 dB at IMD3 = -35 dBc. Moreover, to demonstrate the superior advantage of the proposed configuration, its small-signal and large-signal performance were also compared to that of a single stage common-emitter, a conventional 2-stack, an independently biased 2-stack and a conventional 3-stack configuration. The compared results showed that the independently biased 3-stack is the best candidate among the configurations for various wireless communications applications

Numerical study of spatiotemporal distortions in noncollinear optical parametric chirped-pulse amplifiers

During amplification in a noncollinear optical parametric amplifier the spatial and temporal coordinates of the amplified field are inherently coupled. These couplings or distortions can limit the peak intensity, among other things. In this work, a numerical study of the spatiotemporal distortions in BBO-based noncollinear optical parametric chirped-pulse amplifiers (NOPCPAs) is presented for a wide range of parameters and for different amplification conditions. It is shown that for Gaussian pump beams, gain saturation introduces strong distortions and high conversion efficiency always comes at the price of strong spatiotemporal couplings which drastically reduce the peak intensity even when pulse fronts of the pump and the signal are matched. However, high conversion efficiencies with minimum spatiotemporal distortions can still be achieved with flat-top pump beam profiles

Accurate Settling-Time Modeling and Design Procedures for Two-Stage Miller-Compensated Amplifiers for Switched-Capacitor Circuits

We present modeling techniques for accurate estimation of settling errors in switched-capacitor (SC) circuits built with Miller-compensated operational transconductance amplifiers (OTAs). One distinctive feature of the proposal is the computation of the impact of signal levels (on both the model parameters and the model structure) as they change during transient evolution. This is achieved by using an event-driven behavioral approach that combines small- and large-signal behavioral descriptions and keeps track of the amplifier state after each clock phase. Also, SC circuits are modeled under closed-loop conditions to guarantee that the results remain close to those obtained by electrical simulation of the actual circuits. Based on these models, which can be regarded as intermediate between the more established small-signal approach and full-fledged simulations, design procedures for dimensioning SC building blocks are presented whose targets are system-level specifications (such as ENOB and SNDR) instead of OTA specifications. The proposed techniques allow to complete top-down model-based designs with 0.3-b accuracy.Ministerio de Educación y Ciencia TEC2006-03022Junta de Andalucía TIC-0281

Digital Predistortion in Large-Array Digital Beamforming Transmitters

In this article, we propose a novel digital predistortion (DPD) solution that allows to considerably reduce the complexity resulting from linearizing a set of power amplifiers (PAs) in single-user large-scale digital beamforming transmitters. In contrast to current state-of-the art solutions that assume a dedicated DPD per power amplifier, which is unfeasible in the context of large antenna arrays, the proposed solution only requires a single DPD in order to linearize an arbitrary number of power amplifiers. To this end, the proposed DPD predistorts the signal at the input of the digital precoder based on minimizing the nonlinear distortion of the combined signal at the intended receiver direction. This is a desirable feature, since the resulting emissions in other directions get partially diluted due to less coherent superposition. With this approach, only a single DPD is required, yielding great complexity and energy savings.Comment: 8 pages, Accepted for publication in Asilomar Conference on Signals, Systems, and Computer

Impact of Spatial Filtering on Distortion from Low-Noise Amplifiers in Massive MIMO Base Stations

In massive MIMO base stations, power consumption and cost of the low-noise amplifiers (LNAs) can be substantial because of the many antennas. We investigate the feasibility of inexpensive, power efficient LNAs, which inherently are less linear. A polynomial model is used to characterize the nonlinear LNAs and to derive the second-order statistics and spatial correlation of the distortion. We show that, with spatial matched filtering (maximum-ratio combining) at the receiver, some distortion terms combine coherently, and that the SINR of the symbol estimates therefore is limited by the linearity of the LNAs. Furthermore, it is studied how the power from a blocker in the adjacent frequency band leaks into the main band and creates distortion. The distortion term that scales cubically with the power received from the blocker has a spatial correlation that can be filtered out by spatial processing and only the coherent term that scales quadratically with the power remains. When the blocker is in free-space line-of-sight and the LNAs are identical, this quadratic term has the same spatial direction as the desired signal, and hence cannot be removed by linear receiver processing

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

A fully integrated 24-GHz phased-array transmitter in CMOS

This paper presents the first fully integrated 24-GHz phased-array transmitter designed using 0.18-/spl mu/m CMOS transistors. The four-element array includes four on-chip CMOS power amplifiers, with outputs matched to 50 /spl Omega/, that are each capable of generating up to 14.5 dBm of output power at 24 GHz. The heterodyne transmitter has a two-step quadrature up-conversion architecture with local oscillator (LO) frequencies of 4.8 and 19.2 GHz, which are generated by an on-chip frequency synthesizer. Four-bit LO path phase shifting is implemented in each element at 19.2 GHz, and the transmitter achieves a peak-to-null ratio of 23 dB with raw beam-steering resolution of 7/spl deg/ for radiation normal to the array. The transmitter can support data rates of 500 Mb/s on each channel (with BPSK modulation) and occupies 6.8 mm /spl times/ 2.1 mm of die area

Development of a Low-Noise High Common-Mode-Rejection Instrumentation Amplifier

Several previously used instrumentation amplifier circuits were examined to find limitations and possibilities for improvement. One general configuration is analyzed in detail, and methods for improvement are enumerated. An improved amplifier circuit is described and analyzed with respect to common mode rejection and noise. Experimental data are presented showing good agreement between calculated and measured common mode rejection ratio and equivalent noise resistance. The amplifier is shown to be capable of common mode rejection in excess of 140 db for a trimmed circuit at frequencies below 100 Hz and equivalent white noise below 3.0 nv/square root of Hz above 1000 Hz