Fabrication of wide-IF 200–300 GHz superconductor–insulator–superconductor mixers with suspended metal beam leads formed on silicon-on-insulator

We report on a fabrication process that uses SOI substrates and micromachining techniques to form wide-IF SIS mixer devices that have suspended metal beam leads for rf grounding. The mixers are formed on thin 25 µm membranes of Si, and are designed to operate in the 200–300 GHz band. Potential applications are in tropospheric chemistry, where increased sensitivity detectors and wide-IF bandwidth receivers are desired. They will also be useful in astrophysics to monitor absorption lines for CO at 230 GHz to study distant, highly redshifted galaxies by reducing scan times. Aside from a description of the fabrication process, electrical measurements of these Nb/Al–AlNx/Nb trilayer devices will also be presented. Since device quality is sensitive to thermal excursions, the new beam lead process appears to be compatible with conventional SIS device fabrication technology

Fabrication of Silicon Microneedles for Dermal Interstitial Fluid Extraction in Human Subjects

The goal of this project is to design and develop a fabrication process for silicon microneedle arrays to extract dermal interstitial fluid (ISF) from human skin. ISF is a cell- free, living tissue medium that is known to contain many of the same, clinical biomarkers of general health, stress response and immune status as in blood. However, a significant barrier to adoption of ISF as a diagnostic matrix is the lack of a rapid, minimally invasive method of access and collection for analysis. Microfabricated chips containing arrays of microneedles that can rapidly and painlessly access and collect dermal ISF for bioassay could greatly facilitate point-of-care diagnosis and health monitoring, especially in times of crisis or in austere environments, where drawing venous blood poses an unnecessary infection or biohazard risk. Two different fabrication methods were explored. The first method borrows from a previously reported dicing saw process, where a series of parallel and perpendicular cuts of partial depth are made into a thicker silicon wafer, creating arrays of square columns, which are subsequently sharpened into needles. The second method uses a new, entirely-DRIE process to create the arrays of columns. The columns are sharpened into needles using an isotropic wet etch method (HNA etch) which preferentially enhances etching at the tips and diminishes etching at the base, creating remarkably sharp, conical shaped needles capable of piercing skin. The needles contain holes that pass through the wafer to the opposite side, where they connect to a series of microfluidic channels that lead to a reservoir. The back of the wafer is bonded to glass, providing a hydrophilic cap to the channels, as well as a way to see into the device to detect whether the channels are filling with liquid. The fabrication procedures for both methods are presented, along with 2D- and 3D-rendered schematics for the final devices. Needle geometric shape is crucial to their ability to extract ISF. To determine the appropriate pre-sharpened etched shape, needle columns with a variety of different shapes were designed, produced, sharpened, and examined under a scanning electron microscope. The most promising shapes were selected for further processing and testing. Resulting chips were first bench tested to ensure capillary filling capability, and then tested for ISF collection from human skin. Microneedle arrays which were successfully demonstrated to extract ISF are presented, and the unsuccessful shapes are also shown in the interest of completion. Potential means for improving performance and future research directions are discussed

Reliability analysis of foil substrate based integration of silicon chips

Flexible electronics has attracted significant attention in the recent past due to the booming wearables market in addition to the ever-increasing interest for faster, thinner and foldable mobile phones. Ultra-thin bare silicon ICs fabricated by thinning down standard ICs to thickness below 50 μm are flexible and therefore they can be integrated on or in polymer foils to create flexible hybrid electronic (FHE) components that could be used to replace rigid standard surface mount device (SMD) components. The fabricated FHE components referred as chip foil packages (CFPs) in this work are ideal candidates for FHE system integration owing to their ability to deliver high performance at low power consumption while being mechanically flexible. However, very limited information is available in the literature regarding the reliability of CFPs under static and dynamic bending. The lack of such vital information is a major obstacle impeding their commercialization. With the aim of addressing this issue, this thesis investigates the static and dynamic bending reliability of CFPs. In this scope, the static bending reliability of CFPs has been investigated in this thesis using flexural bending tests by measuring their fracture strength. Then, Finite Element Method (FEM) simulations have been implemented to calculate the fracture stress of ultra-thin flexible silicon chips where analytical formulas may not be applied. After calculating the fracture stress from FEM simulations, the enhancement in robustness of ultra-thin chips (UTCs) against external load has also been proved and quantified with further experimental investigations. Besides, FEM simulations have also been used to analyse the effect of Young’s Modulus of embedding materials on the robustness of the embedded UTCs. Furthermore, embedding the UTCs in polymer layers has also been experimentally proven to be an effective solution to reduce the influence of thinning and dicing induced damages on the robustness of the embedded UTCs. Traditional interconnection techniques such as wire bonding may not be implemented to interconnect ultra-thin silicon ICs owing to the high mechanical forces involved in the processes that would crack the chips. Therefore, two novel interconnection methods namely (i) flip-chip bonding with Anisotropic Conductive Adhesive (ACA) and (ii) face-up direct metal interconnection have been implemented in this thesis to interconnect ultra-thin silicon ICs to the corresponding interposer patterns on foil substrates. The CFP samples thus fabricated were then used for the dynamic bending reliability investigations. A custom-built test equipment was developed to facilitate the dynamic bending reliability investigations of CFPs. Experimental investigations revealed that the failure of CFPs under dynamic bending was caused mainly by the cracking of the redistribution layer (RDL) interconnecting the chip and the foil. Furthermore, it has also been shown that the CFPs are more vulnerable to repeated compressive bending than to repeated tensile bending. Then, the influence of dimensional factors such as the thickness of the chip as well as the RDL on the dynamic bending reliability of CFPs have also been studied. Upon identifying the plausible cause behind the cracking of the RDL leading to the failure of the CFPs, two methods to improve the dynamic bending reliability of the RDL have been suggested and demonstrated with experimental investigations. The experimental investigations presented in this thesis adds some essential information to the state-of-the-art concerning the static and the dynamic bending reliability of UTCs integrated in polymer foils that are not yet available in the literature and aids to establish in-depth knowledge of mechanical reliability of the components required for manufacturing future FHE systems. The strategies devised to enhance the robustness of UTCs and CFPs could serve as guidelines for fabricating reliable FHE components and systems

Technologies for 3D Heterogeneous Integration

3D-Integration is a promising technology towards higher interconnect densities and shorter wiring lengths between multiple chip stacks, thus achieving a very high performance level combined with low power consumption. This technology also offers the possibility to build up systems with high complexity just by combining devices of different technologies. For ultra thin silicon is the base of this integration technology, the fundamental processing steps will be described, as well as appropriate handling concepts. Three main concepts for 3D integration have been developed at IZM. The approach with the greatest flexibility called Inter Chip Via - Solid Liquid Interdiffusion (ICV-SLID) is introduced. This is a chip-to-wafer stacking technology which combines the advantages of the Inter Chip Via (ICV) process and the solid-liquid-interdiffusion technique (SLID) of copper and tin. The fully modular ICV-SLID concept allows the formation of multiple device stacks. A test chip was designed and the total process sequence of the ICV-SLID technology for the realization of a three-layer chip-to-wafer stack was demonstrated. The proposed wafer-level 3D integration concept has the potential for low cost fabrication of multi-layer high-performance 3D-SoCs and is well suited as a replacement for embedded technologies based on monolithic integration. To address yield issues a wafer-level chip-scale handling is presented as well, to select known-good dies and work on them with wafer-level process sequences before joining them to integrated stacks.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

Embedding and assembly of ultrathin chips in multilayer flex boards

Dieser Beitrag ist mit Zustimmung des Rechteinhabers aufgrund einer (DFG geförderten) Allianz- bzw. Nationallizenz frei zugänglich.This publication is with permission of the rights owner freely accessible due to an Alliance licence and a national licence (funded by the DFG, German Research Foundation) respectively.Purpose – The purpose of this paper is to present results from the EC funded project SHIFT (Smart High Integration Flex Technologies) on the embedding in and the assembly on flex substrates of ultrathin chips. Design/methodology/approach – Methods to embed chips in flex include flip-chip assembly and subsequent lamination, or the construction of a separate ultra-thin chip package (UTCP) using spin-on polyimides and thin-film metallisation technology. Thinning and separation of the chips is done using a “dicing-by-thinning” method. Findings – The feasibility of both chip embedding methods has been demonstrated, as well as that of the chip thinning method. Lamination of four layers of flex with ultrathin chips could be achieved without chip breakage. The UTCP technology results in a 60 mm package where also the 20mm thick chip is bendable. Research limitations/implications – Further development work includes reliability testing, embedding of the UTCP in conventional flex, and construction of functional demonstrators using the developed technologies. Originality/value – Thinning down silicon chips to thicknesses of 25mm and lower is an innovative technology, as well as assembly and embedding of these chips in flexible substrates.EC/FP6/EU/507745/Smart high-integration flex technologies/SHIF

Integration of Bulk Piezoelectric Materials into Microsystems.

Bulk piezoelectric ceramics, compared to deposited piezoelectric thin-films, provide greater electromechanical coupling and charge capacity, which are highly desirable in many MEMS applications. In this thesis, a technology platform is developed for wafer-level integration of bulk piezoelectric substrates on silicon, with a final film thickness of 5-100μm. The characterized processes include reliable low-temperature (200˚C) AuIn diffusion bonding and parylene bonding of bulk-PZT on silicon, wafer-level lapping of bulk-PZT with high-uniformity (±0.5μm), and low-damage micro-machining of PZT films via dicing-saw patterning, laser ablation, and wet-etching. Preservation of ferroelectric and piezoelectric properties is confirmed with hysteresis and piezo-response measurements. The introduced technology offers higher material quality and unique advantages in fabrication flexibility over existing piezoelectric film deposition methods. In order to confirm the preserved bulk properties in the final film, diaphragm and cantilever beam actuators operating in the transverse-mode are designed, fabricated and tested. The diaphragm structure and electrode shapes/sizes are optimized for maximum deflection through finite-element simulations. During tests of fabricated devices, greater than 12μmPP displacement is obtained by actuation of a 1mm2 diaphragm at 111kHz with <7mW power consumption. The close match between test data and simulation results suggests that the piezoelectric properties of bulk-PZT5A are mostly preserved without any necessity of repolarization. Three generations of resonant vibration energy harvesters are designed, simulated and fabricated to demonstrate the competitive performance of the new fabrication process over traditional piezoelectric deposition systems. An unpackaged PZT/Si unimorph harvester with 27mm3 active device volume produces up to 205μW at 1.5g/154Hz. The prototypes have achieved the highest figure-of-merits (normalized-power-density × bandwidth) amongst previously reported inertial energy harvesters. The fabricated energy harvester is utilized to create an autonomous energy generation platform in 0.3cm3 by system-level integration of a 50-80% efficient power management IC, which incorporates a supply-independent bias circuitry, an active diode for low-dropout rectification, a bias-flip system for higher efficiency, and a trickle battery charger. The overall system does not require a pre-charged battery, and has power consumption of <1μW in active-mode (measured) and <5pA in sleep-mode (simulated). Under 1g vibration at 155Hz, a 70mF ultra-capacitor is charged from 0V to 1.85V in 50 minutes.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/1/aktakka_3.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/2/aktakka_2.pdfhttp://deepblue.lib.umich.edu/bitstream/2027.42/91479/3/aktakka_1.pd

Die separation strength for deep reactive ion etched wafers.

In the electronic and microfabrication industry, die separation is one of the most critical steps in producing an undamaged, stand-alone micro-scale device. For silicon based devices, it is the predominant step governing resistance to die failure by mechanical fracture. Traditional separation methods include the use of dicing saws and/or backside grinding to dice-by-thinning. Excessive forces, vibrations, and surface contact involved with these methods can cause undesirable side-wall chipping and microcracking, which often translates to inoperable devices. Deep Reactive Ion Etching (DRIE) offers an alternative technique for die separation with less mechanical force. The DRIE process may be used to either introduce notches in one uniform step that allow for die separation via fracture in three-point bending, or to directly separate the dies by etching completely through the substrate. This work presents an analysis of the stress concentrations due to DRIE etched notches and the bending stress required to achieve die separation. The defect rate and die strength associated with DRIE-based die separated is compared with traditional saw methods for a variety of notch depths. Results indicate that the DRIE-based separation technique offers modest advantages over the traditional methods, but can also greatly reduce strength if the protective mask is over etched. It will also show that shallow trenches formed by a mechanical dicing saw resulted in stronger die than deeper trenches

Thermal dissipation improvement by new technology approach: study, development and characterization

Semiconductor manufacturing requires a silicon substrate to build devices on its front side. The wafer must be thick enough to ensure a stable support during the processing steps. Since the active region of a semiconductor device is limited at the substrate surface, there is a large unused material amount. The material excess causes heat increasing during the operation of the devices. Once the Frond End of Line is completed, the excess material must be removed. Nowadays, there are different thinning techniques adopted in order to reduce the thermal resistance. The thesis project idea is the thermal dissipation improvement with a different approach: instead of reducing the wafer thickness, the adopted technology is exploiting the excess material as a heat sink. The realization of this intrinsic heat sink is achieved by the developing of a suitable process flow, which involves the selective dry etching of the silicon bulk and the subsequent electrodeposition of thick copper. This new process flow offers the advantage of maintaining the wafer “self-support” and allow working with already existing technologies saving on both dedicated thinning technologies and handling technologies. Furthermore, this new approach permits the thermal resistance improvement of semiconductor devices if compared to the standard devices

Modeling of CMOS devices and circuits on flexible ultrathin chips

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18-μm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20 μm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch)