Analyses of parasitic capacitance effects and flicker noise of the DAC capacitor array for high resolution SAR ADCs

Copyright © 2018 Inderscience Enterprises Ltd. This paper analyses the effects of parasitic capacitances of unit capacitors on the accuracy and the noise performance of the DAC capacitor array in a SAR ADC, showing that thermal noise of the array decreases while gain error is introduced. The gain error is almost independent of the number of bits, but the dynamic range of the high resolution ADC is severely reduced due to the gain error. The post-layout parasitic capacitance analysis of a 10-bit poly-poly array shows a large difference between the top-plate and bottom-plate parasitic capacitances so that the gain error can be decreased by 152 times when top-plates are connected together as the output node of the array. The switching transistors’ flicker noise calculation for a 10-bit and an 18-bit SAR ADC shows that flicker noise can be safely ignored for 10-bit 1MSPS SAR, but should be considered for the higher resolution SAR ADCs

Implementation of a 200 MSps 12-bit SAR ADC

Analog-to-digital converters (ADCs) with high conversion frequency, often based on pipelined architectures, are used for measuring instruments, wireless communication and video applications. Successive approximation register (SAR) converters offer a compact and power efficient alternative but the conversion speed is typically designed for lower frequencies. In this thesis a low-power 12-bit 200 MSps SAR ADC based on charge redistribution was designed for a 28 nm CMOS technology. The proposed design uses an efficient SAR algorithm (merged capacitor switching procedure) to reduce power consumption due to capacitor charging by 88 % compared to a conventional design, as well as reducing the total capacitor area by half. Sampling switches were bootstrapped for increased linearity compared to simple transmission gates. Another feature of the low power design is a fully-dynamic comparator which does not require a preamplifier. Pre-layout simulations of the SAR ADC with 800 MHz input frequency shows an SNDR of 64.8 dB, corresponding to an ENOB of 10.5, and an SFDR of 75.3 dB. The total power consumption is 1.77 mW with an estimated value of 500 W for the unimplemented digital logic. Calculation of the Schreier figure-of-merit was done with an input signal at the Nyquist frequency. The simulated SNDR, SFDR and power equals 69.5 dB, 77.3 dB and 1.9 mW respectively, corresponding to a figure-of merit of 176.6 dB.Från analogt till digitalt - snabba och strömsnåla omvandlare Dagens digitala samhälle ställer höga krav på prestanda och effektivitet. I samarbete med Ericsson i Lund har en krets för signalomvandling utvecklats. Genom smart design uppnås hög hastighet och låg strömförbrukning som ligger i forskningens framkant. Från analogt till digitalt Ett viktigt byggblock för telekommunikation och videoapplikationer är så kallade A/D-omvandlare, som översätter mellan analoga signaler (till exempel ljud) och digitala signaler bestående av ettor och nollor. En väldigt effektiv metod för A/D-omvandling bygger på så kallad successiv approximation. Metoden innebär att signalen som ska omvandlas jämförs med en referensnivå, som stegvis justeras för att närma sig signalens värde. Till slut har man en tillräckligt god uppskattning av värdet som ska mätas. Just en sådan omvandlare har utvecklats med höga krav på hastighet och energiförbrukning. Detta gjordes genom datorsimuleringar av modeller som beskriver kretsen. Referensnivån skapas ofta genom att styra ett nätverk som lagrar elektrisk laddning. Omvandlingens noggrannhet, eller upplösning, beror på hur många nivåer som finns tillgängliga det vill säga hur nära signalens värde man kan komma. I den designade kretsen finns hela 4096 nivåer! Det finns många källor till osäkerhet i systemet, bland annat hur exakta referensnivåerna är och hur bra jämförelsen med insignalen kan göras. Eftersom dessa eventuellt kan leda till en försämring av omvandlingens noggrannhet måste alla delar i kretsen utformas med detta i åtanke. Höga hastigheter Eftersom det krävs många steg för referensnivån att närma sig signalens värde är den maximala omvandlingshastigheten ofta begränsad. Med teknikens utveckling öppnas nya möjligheter i takt med att mikrochippens enskilda komponenter blir snabbare. Modern forskning visar att omvandlare baserade på successiv approximation kan uppnå hastigheter på flera miljoner mätvärden varje sekund, vilket även den utvecklade kretsen klarar av. Effektiv design Nya metoder för successiv approximation möjliggör stora besparingar när det gäller effektförbrukning, till exempel genom att effektivisera upp- och urladdningen av nätverket. Genom små ändringar kunde nätverkets energiförbrukning minskas med över 90 % samtidigt som dess area halverades. Eftersom produktionskostnaden för integrerade kretsar är hög medför varje minskning av kretsens area att kostnaden sjunker

Design techniques for successive approximation register analog-to-digital converters

Successive approximation register analog-to-digital converters (SAR ADCs) have been widely used for medium-speed, medium-resolution applications due to their excellent power efficiency and digital compatibility. Recently, SAR ADCs are also penetrating into the applications which have been earlier dominated by delta-sigma ADCs and pipeline ADCs. However, the resolution of SAR ADCs is limited by component mismatch, and their speed is generally slow due to serial operation. In this work, several system innovations and design techniques are investigated for SAR ADCs. First, a semi-synchronous clocking is proposed to optimize the comparator resolving time and DAC settling time in the SAR conversion. Simulations show a 40% speed-up compared with conventional synchronous processing. A self-calibration technique to correct the capacitor mismatch error is also introduced. The proposed calibration algorithm is verified to be insensitive to the non-idealities in the calibration DACs

An implantable mixed-signal CMOS die for battery-powered in vivo blowfly neural recordings

© 2018 A mixed-signal die containing two differential input amplifiers, a multiplexer and a 50 KSPS, 10-bit SAR ADC, has been designed and fabricated in a 0.35 μm CMOS process for in vivo neural recording from freely moving blowflies where power supplied voltage drops quickly due to the space/weight limited insufficient capacity of the battery. The designed neural amplifier has a 66 + dB gain, 0.13 Hz-5.3 KHz bandwidth and 0.39% THD. A 20% power supply voltage drop causes only a 3% change in amplifier gain and 0.9-bit resolution degrading for SAR ADC while the on-chip data modulation reduces the chip size, rendering the designed chip suitable for battery-powered applications. The fabricated die occupies 1.1 mm2 while consuming 238 μW, being suitable for implantable neural recordings from insects as small as a blowfly for electrophysiological studies of their sensorimotor control mechanisms. The functionality of the die has been validated by recording the signals from identified interneurons in the blowfly visual system

High speed – energy efficient successive approximation analog to digital converter using tri-level switching

This thesis reports issues and design methods used to achieve high-speed and high-resolution Successive Approximation Register analog to digital converters (SAR ADCs). A major drawback of this technique relates to the mismatch in the binary ratios of capacitors which causes nonlinearity. Another issue is the use of large capacitors due to nonlinear effect of parasitic capacitance. Nonlinear effect of capacitor mismatch is investigated in this thesis. Based on the analysis, a new Tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over conventional SAR ADC, which is the lowest compared to the previously reported schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% compared with the conventional SAR architecture. A new correction method to solve metastability error of comparator based on a novel design approach is proposed which reduces the required settling time about 1.1τ for each conversion cycle. Based on the above proposed methods two SAR ADCs: an 8-bit SAR ADC with 50MS/sec sampling rate, and a 10-bit SAR split ADC with 70 MS/sec sampling rate have been designed in 0.18μm Silterra complementary metal oxide semiconductor (CMOS) technology process which works at 1.2V supply voltage and input voltage of 2.4Vp-p. The 8-bit ADC digitizes 25MHz input signal with 48.16dB signal to noise and distortion ratio (SNDR) and 52.41dB spurious free dynamic range (SFDR) while consuming about 589μW. The figure of merit (FOM) of this ADC is 56.65 fJ/conv-step. The post layout of the 10-bit ADC with 1MHz input frequency produces SNDR, SFDR and effective number of bits (ENOB) of 57.1dB, 64.05dB and 9.17Bit, respectively, while its DNL and INL are -0.9/+2.8 least significant bit (LSB) and -2.5/+2.7 LSB, respectively. The total power consumption, including digital, analog and reference power, is 1.6mW. The FOM is 71.75fJ/conv. step

Free Level Threshold Zone (FLTZ) Logic For Mixed Analog-Digital Closed Loop Circuitry [TK7887.6. N335 2008 f rb].

Para penyelidik sentiasa mencari cara-cara penambahbaikan kaedah antara muka antara domain Analog dan Digital. Researchers have always look for ways to improve the interfacing method between the Analog and Digital domain

Ultra-low Power Circuits for Internet of Things (IOT)

Miniaturized sensor nodes offer an unprecedented opportunity for the semiconductor industry which led to a rapid development of the application space: the Internet of Things (IoT). IoT is a global infrastructure that interconnects physical and virtual things which have the potential to dramatically improve people's daily lives. One of key aspect that makes IoT special is that the internet is expanding into places that has been ever reachable as device form factor continue to decreases. Extremely small sensors can be placed on plants, animals, humans, and geologic features, and connected to the Internet. Several challenges, however, exist that could possibly slow the development of IoT. In this thesis, several circuit techniques as well as system level optimizations to meet the challenging power/energy requirement for the IoT design space are described. First, a fully-integrated temperature sensor for battery-operated, ultra-low power microsystems is presented. Sensor operation is based on temperature independent/dependent current sources that are used with oscillators and counters to generate a digital temperature code. Second, an ultra-low power oscillator designed for wake-up timers in compact wireless sensors is presented. The proposed topology separates the continuous comparator from the oscillation path and activates it only for short period when it is required. As a result, both low power tracking and generation of precise wake-up signal is made possible. Third, an 8-bit sub-ranging SAR ADC for biomedical applications is discussed that takes an advantage of signal characteristics. ADC uses a moving window and stores the previous MSBs voltage value on a series capacitor to achieve energy saving compared to a conventional approach while maintaining its accuracy. Finally, an ultra-low power acoustic sensing and object recognition microsystem that uses frequency domain feature extraction and classification is presented. By introducing ultra-low 8-bit SAR-ADC with 50fF input capacitance, power consumption of the frontend amplifier has been reduced to single digit nW-level. Also, serialized discrete Fourier transform (DFT) feature extraction is proposed in a digital back-end, replacing a high-power/area-consuming conventional FFT.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137157/1/seojeong_1.pd