Saturn integrated circuit reliability test program Final report, 28 Jun. 1966 - 1 Jul. 1967

Literature survey and test program to study reliability of linear integrated circuit

Design and qualification of the SEU/TD Radiation Monitor chip

This report describes the design, fabrication, and testing of the Single-Event Upset/Total Dose (SEU/TD) Radiation Monitor chip. The Radiation Monitor is scheduled to fly on the Mid-Course Space Experiment Satellite (MSX). The Radiation Monitor chip consists of a custom-designed 4-bit SRAM for heavy ion detection and three MOSFET's for monitoring total dose. In addition the Radiation Monitor chip was tested along with three diagnostic chips: the processor monitor and the reliability and fault chips. These chips revealed the quality of the CMOS fabrication process. The SEU/TD Radiation Monitor chip had an initial functional yield of 94.6 percent. Forty-three (43) SEU SRAM's and 14 Total Dose MOSFET's passed the hermeticity and final electrical tests and were delivered to LL

The ALICE TPC, a large 3-dimensional tracking device with fast readout for ultra-high multiplicity events

The design, construction, and commissioning of the ALICE Time-Projection Chamber (TPC) is described. It is the main device for pattern recognition, tracking, and identification of charged particles in the ALICE experiment at the CERN LHC. The TPC is cylindrical in shape with a volume close to 90 m^3 and is operated in a 0.5 T solenoidal magnetic field parallel to its axis. In this paper we describe in detail the design considerations for this detector for operation in the extreme multiplicity environment of central Pb--Pb collisions at LHC energy. The implementation of the resulting requirements into hardware (field cage, read-out chambers, electronics), infrastructure (gas and cooling system, laser-calibration system), and software led to many technical innovations which are described along with a presentation of all the major components of the detector, as currently realized. We also report on the performance achieved after completion of the first round of stand-alone calibration runs and demonstrate results close to those specified in the TPC Technical Design Report.Comment: 55 pages, 82 figure

Development of reliability methodology for systems engineering. Volume II - Application - Design reliability analysis of a 250 volt-ampere static inverter Final report

Design stage reliability analysis application to static inverte

Index to 1984 NASA Tech Briefs, volume 9, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1984 Tech B Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences

Advanced Computer Dormant Reliability Study Final Report

Reliability of integrated circuits and discrete components of electronics for computer and dormant module for Minuteman

A study of high-speed AD and DA converters using redundancy techniques Interim report, May 10, 1963 - May 9, 1964

High speed analog-to-digital converters compared using redundancy encoding technique

Product assurance technology for custom LSI/VLSI electronics

The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification

Flexible Ultralow-Power Sensor Interfaces for E-Skin

Thin-film electronics has hugely benefitted from low-cost processes, large-area processability, and multi-functionality. This has not only stimulated innovation in display and sensor technology, but has also demonstrated great potential for integration of components for human-machine interfaces. For electronics to be deployed as sensor interfaces and signal processing, the quest for low power is compelling due to the inherently limited battery lifetime. This review will present the state-of-the-art in thin film electronics and demonstrate examples of low-cost printable transistors and biosensors that are flexible/stretchable for wearable and other applications. Ultralow power design for thin-film transistors will be discussed from the standpoint of reducing both operating voltage and operating current, taking into account the challenges in meeting frequency requirements. Compact models for circuit design will be reviewed along with new insights into ultralow power transistors and high gain amplifier circuits. Finally, a concept for an integrated system comprising sensors and interfacing circuits will be demonstrated, which has the potential to enable battery-less operation.EPSRC under Project EP/M013650/1 EU under Projects DOMINO 645760, 1D-NEON 685758 and BET-EU 692373 IEEE Electron Devices Society PhD Student Fellowship China Scholarship Counci

Neurofly 2008 abstracts : the 12th European Drosophila neurobiology conference 6-10 September 2008 Wuerzburg, Germany

This volume consists of a collection of conference abstracts