Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

A novel low-temperature growth method of silicon structures and application in flash memory.

Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon

Forensic applications of atomic force microscopy

The first project undertaken was to develop a currently non-existent forensic technique -- data recovery from damaged SIM cards. SIM cards hold data valuable to a forensic investigator within non-volatile EEPROM/flash memory arrays. This data has been proven to be able to withstand temperatures up to 500°C, surviving such scenarios as house fires or criminal evidence disposal. A successful forensically-sound sample extraction, mounting and backside processing methodology was developed to expose the underside of a microcontroller circuit's floating gate transistor tunnel oxide, allowing probing via AFM-based electrical scanning probe techniques. Scanning Kelvin probe microscopy has thus far proved capable of detecting the presence of stored charge within the floating gates beneath the thin tunnel oxide layer, to the point of generating statistical distributions reflecting the threshold voltage states of the transistors. The second project covered the novel forensic application of AFM as a complimentary technique to SEM examination of quartz grain surface textures. The analysis and interpretation of soil/sediment samples can provide indications of their provenance, and enable exclusionary comparisons to be made between samples pertinent to a forensic investigation. Multiple grains from four distinct sample sets were examined with the AFM, and various statistical figures of merit were derived. Canonical discriminant analysis was used to assess the discriminatory abilities of these statistical variables to better characterise the use of AFM results for grain classification. The final functions correctly classified 65.3% of original grouped cases, with the first 3 discriminant functions used in the analysis (Wilks' Lambda=0.336, p=0.000<0.01). This degree of discrimination shows a great deal of promise for the AFM as a quantitative corroborative technique to traditional SEM grain surface examination

Low Energy Ion Beam Synthesis of SiNanocrystals for Nonvolatile Memories – Modeling and Process Simulations

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Low Energy Ion Beam Synthesis of Si Nanocrystals for Nonvolatile Memories - Modeling and Process Simulations

Metal-Oxide-Silicon Field-Effect-Transistors with a layer of electrically isolated Si nanocrystals (NCs) embedded in the gate oxide are known to improve conventional floating gate flash memories. Data retention, program and erase speeds as well as the memory operation voltages can be substantially improved due to the discrete charge storage in the isolated Si NCs. Using ion beam synthesis, Si NCs can be fabricated along with standard CMOS processing. The optimization of the location and size of ion beam synthesized Si NCs requires a deeper understanding of the mechanisms involved, which determine (i) the built-up of Si supersaturation by high-fluence ion implantation and (ii) NC formation by phase separation. For that aim, process simulations have been conducted that address both aspects on a fundamental level and, on the other hand, are able to avoid tedious experiments. The built-up of a Si supersaturation by high-fluence ion implantation were studied using dynamic binary collision calculations with TRIDYN and have lead to a prediction of Si excess depth profiles in thin gate oxides of a remarkable quality. These simulations include in a natural manner high fluence implantation effects as target erosion by sputtering, target swelling and ion beam mixing. The second stage of ion beam synthesis is modeled with the help of a tailored kinetic Monte Carlo code that combines a detailed kinetic description of phase separation on atomic level with the required degree of abstraction that is necessary to span the timescales involved. Large ensembles of Si NCs were simulated reaching the late stages of NC formation and dissolution at simulation sizes that allowed a direct comparison with experimental studies, e.g. with electron energy loss resolved TEM investigations. These comparisons reveal a nice degree of agreement, e.g. in terms of predicted and observed precipitate morphologies for different ion fluences. However, they also point clearly onto impact of additional external influences as, e.g., the oxidation of implanted Si by absorbed humidity, which was identified with the help of these process simulations. Moreover, these simulations are utilized as a general tool to identify optimum processing regimes for a tailored Si NC formation for NC memories. It is shown that key properties for NC memories as the tunneling distance from the transistor channel to the Si NCs, the NC morphology, size and density can be adjusted accurately despite of the involved degree of self-organization. Furthermore, possible lateral electron tunneling between neighboring Si NCs is evaluated on the basis of the performed kinetic Monte Carlo simulations

Gestión de jerarquías de memoria híbridas a nivel de sistema

Tesis inédita de la Universidad Complutense de Madrid, Facultad de Informática, Departamento de Arquitectura de Computadoras y Automática y de Ku Leuven, Arenberg Doctoral School, Faculty of Engineering Science, leída el 11/05/2017.In electronics and computer science, the term ‘memory’ generally refers to devices that are used to store information that we use in various appliances ranging from our PCs to all hand-held devices, smart appliances etc. Primary/main memory is used for storage systems that function at a high speed (i.e. RAM). The primary memory is often associated with addressable semiconductor memory, i.e. integrated circuits consisting of silicon-based transistors, used for example as primary memory but also other purposes in computers and other digital electronic devices. The secondary/auxiliary memory, in comparison provides program and data storage that is slower to access but offers larger capacity. Examples include external hard drives, portable flash drives, CDs, and DVDs. These devices and media must be either plugged in or inserted into a computer in order to be accessed by the system. Since secondary storage technology is not always connected to the computer, it is commonly used for backing up data. The term storage is often used to describe secondary memory. Secondary memory stores a large amount of data at lesser cost per byte than primary memory; this makes secondary storage about two orders of magnitude less expensive than primary storage. There are two main types of semiconductor memory: volatile and nonvolatile. Examples of non-volatile memory are ‘Flash’ memory (sometimes used as secondary, sometimes primary computer memory) and ROM/PROM/EPROM/EEPROM memory (used for firmware such as boot programs). Examples of volatile memory are primary memory (typically dynamic RAM, DRAM), and fast CPU cache memory (typically static RAM, SRAM, which is fast but energy-consuming and offer lower memory capacity per are a unit than DRAM). Non-volatile memory technologies in Si-based electronics date back to the 1990s. Flash memory is widely used in consumer electronic products such as cellphones and music players and NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. The rapid increase of leakage currents in Silicon CMOS transistors with scaling poses a big challenge for the integration of SRAM memories. There is also the case of susceptibility to read/write failure with low power schemes. As a result of this, over the past decade, there has been an extensive pooling of time, resources and effort towards developing emerging memory technologies like Resistive RAM (ReRAM/RRAM), STT-MRAM, Domain Wall Memory and Phase Change Memory(PRAM). Emerging non-volatile memory technologies promise new memories to store more data at less cost than the expensive-to build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. These new memory technologies combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the non-volatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. The research and information on these Non-Volatile Memory (NVM) technologies has matured over the last decade. These NVMs are now being explored thoroughly nowadays as viable replacements for conventional SRAM based memories even for the higher levels of the memory hierarchy. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional(3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years...En el campo de la informática, el término ‘memoria’ se refiere generalmente a dispositivos que son usados para almacenar información que posteriormente será usada en diversos dispositivos, desde computadoras personales (PC), móviles, dispositivos inteligentes, etc. La memoria principal del sistema se utiliza para almacenar los datos e instrucciones de los procesos que se encuentre en ejecución, por lo que se requiere que funcionen a alta velocidad (por ejemplo, DRAM). La memoria principal está implementada habitualmente mediante memorias semiconductoras direccionables, siendo DRAM y SRAM los principales exponentes. Por otro lado, la memoria auxiliar o secundaria proporciona almacenaje(para ficheros, por ejemplo); es más lenta pero ofrece una mayor capacidad. Ejemplos típicos de memoria secundaria son discos duros, memorias flash portables, CDs y DVDs. Debido a que estos dispositivos no necesitan estar conectados a la computadora de forma permanente, son muy utilizados para almacenar copias de seguridad. La memoria secundaria almacena una gran cantidad de datos aun coste menor por bit que la memoria principal, siendo habitualmente dos órdenes de magnitud más barata que la memoria primaria. Existen dos tipos de memorias de tipo semiconductor: volátiles y no volátiles. Ejemplos de memorias no volátiles son las memorias Flash (algunas veces usadas como memoria secundaria y otras veces como memoria principal) y memorias ROM/PROM/EPROM/EEPROM (usadas para firmware como programas de arranque). Ejemplos de memoria volátil son las memorias DRAM (RAM dinámica), actualmente la opción predominante a la hora de implementar la memoria principal, y las memorias SRAM (RAM estática) más rápida y costosa, utilizada para los diferentes niveles de cache. Las tecnologías de memorias no volátiles basadas en electrónica de silicio se remontan a la década de1990. Una variante de memoria de almacenaje por carga denominada como memoria Flash es mundialmente usada en productos electrónicos de consumo como telefonía móvil y reproductores de música mientras NAND Flash solid state disks(SSDs) están progresivamente desplazando a los dispositivos de disco duro como principal unidad de almacenamiento en computadoras portátiles, de escritorio e incluso en centros de datos. En la actualidad, hay varios factores que amenazan la actual predominancia de memorias semiconductoras basadas en cargas (capacitivas). Por un lado, se está alcanzando el límite de integración de las memorias Flash, lo que compromete su escalado en el medio plazo. Por otra parte, el fuerte incremento de las corrientes de fuga de los transistores de silicio CMOS actuales, supone un enorme desafío para la integración de memorias SRAM. Asimismo, estas memorias son cada vez más susceptibles a fallos de lectura/escritura en diseños de bajo consumo. Como resultado de estos problemas, que se agravan con cada nueva generación tecnológica, en los últimos años se han intensificado los esfuerzos para desarrollar nuevas tecnologías que reemplacen o al menos complementen a las actuales. Los transistores de efecto campo eléctrico ferroso (FeFET en sus siglas en inglés) se consideran una de las alternativas más prometedores para sustituir tanto a Flash (por su mayor densidad) como a DRAM (por su mayor velocidad), pero aún está en una fase muy inicial de su desarrollo. Hay otras tecnologías algo más maduras, en el ámbito de las memorias RAM resistivas, entre las que cabe destacar ReRAM (o RRAM), STT-RAM, Domain Wall Memory y Phase Change Memory (PRAM)...Depto. de Arquitectura de Computadores y AutomáticaFac. de InformáticaTRUEunpu

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields

Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits

Title from PDF of title page viewed August 28, 2017Dissertation advisor: Masud H. ChowdhuryVitaIncludes bibliographical references (pages 120-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2016Floating gate transistor is the basic building block of non-volatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. Recently there has been a surge of interest to introduce a new generation of memory devices using graphene nanotechnology. In this paper we present a new floating gate transistor (FGT) design based on multilayer graphene nanoribbon (MLGNR) and carbon nanotube (CNT). In the proposed graphene based floating gate transistor (GFGT) a multilayer structure of graphene nanoribbon (GNR) would be used as the channel of the field effect transistor (FET) and a layer of CNTs would be used as the floating gate. We have performed an analysis of the charge accumulation mechanism in the floating gate and its dependence on the applied terminal voltages. Based on our analysis we have observed that proposed graphene based floating gate transistor could be operated at a reduced voltage compared to conventional silicon based floating gate devices. We have presented detail analysis of the operation and the programming and erasing processes of the proposed FGT, dependency of the programming and erasing current density on different parameters, impact of scaling the thicknesses of the control and tunneling oxides. These analyses are done based on the equivalent capacitance model of the device. We have analyze the programming and erasing by the tunneling current mechanism in the proposed graphene-CNT floating gate transistor. In this paper, we have investigated the mechanism of programming current and the factors that would influence this current and the behavior of the proposed floating gate transistor. The analysis reveals that programming is a strong function of the high field induced by the control gate, and the thicknesses of the control oxide and the tunnel oxide. With the growing demand for nonvolatile flash memory devices and increasing limitations of silicon technologies, there has been a growing interest to develop emerging flash memory by using alternative nanotechnology. The proposed FGT device for nonvolatile flash memory contains an MLGNR channel and a CNT floating gate with SiO₂ as the tunnel oxide. In this paper, we have presented detail analysis of the electrical properties and performance characteristics of the proposed FGT device. We have focused on the following aspects: current voltage (I-V) characteristics, threshold voltage variation (∆VTH), programming, erasing and reading power consumptions compared to the existing FGTs, and layer-by-layer current voltage characteristics comparison of the proposed GFGT device. To realize graphene field effect transistor (GFET), a general model is developed, validated and analyzed. This model is also used to estimate graphene channel behavior of the proposed GFGT. Reliability is the major concern of the Flash memory technology. We have analyzed retention characteristics of the proposed GFGT. We also have developed a radiation harness test model for the Si-FGT by using VTH variation principle due to the radiation exposure. Flash memory experiences adverse effects due to radiation. These effects can be raised in terms of doping, feature size, supply voltages, layout, shielding. The operating point shift of the device forced to enter the logically-undefined region and cause upset and data errors under radiation exposure. In this research, the threshold voltage shift of the floating gate transistor (FGT) is analyzed by a mathematical model. Molybdenum disulfide (MoS2) based field effect transistor is considered as one of the promising future logic devices. Many other nanoelectronic devices based on MoS2 are currently under investigation. However, the challenge of providing reliable and efficient contact between 2D materials like MoS2 and the metal is still unresolved. The contact resistance between metal and MoS2 limits the application of MoS2 in current semiconductor technologies. In this paper, a detail analysis of metal-MoS2 contact has been presented. Specific contributions of this work are:investigation of the physical, material and electrical parameters that would determine the contact properties, analysis of the combined impact of the top and back gates for the first time, modeling of the crucial metal-MoS2 contact parameters, such as, sheet resistance (RSh), contact resistivity (ρc), contact resistance (RC) and transfer length (LT), investigation of the ways to incorporate the developed contact model into the electronic design automation (EDA) tools and investigation of different contact materials for the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an intermediate state. It is important to realize CAD design challenges of the 2.5D-IC/3D-IC when minimum spacing interconnects are used. The major contributions of this research work are as follows. Previously, for the small scale experimental purpose, small numbers (10-20) of TSVs, interconnects, bumps are fabricated together by hand calculation. However in the real 3D-IC design, thousands of TSVs, interconnects, bumps are reuired. Therefore, an automated CAD solution is required to provide precise physical design and verification. Therefore, a solid CAD solution is provided here. Compatible with 40nm-technology design, which enables the Silicon Interposer to integrate with the digital, analog and RF dies together. Dimensions and spacing of the TSV and Bump are optimized by the 3D EM full wave field solver. To our best knowledge, at the interposer level, this design reports the most dense and well-defined RDL, TSV and micro-bump co-design on Silicon Interposer, which will be used for 2.5D-IC.Introduction and background -- Proposed Graphene Based Flash Memory -- Physical and Electrical Parameters of the Proposed Graphene Flash Memory Device -- Programming and Erasing Operation of the Proposed Graphene Flash Memory Device -- Reliability Analysis of the Proposed Graphene Flash Memory Device -- Radiation Hardness Analysis of the Floating Gate Transistor -- Benchmarking of the Proposed Graphene Flash Memory Device -- Graphene Field Effect Transistor (GFET) Generalized Model -- MoS2 FET Device and Contact Characterization and Modelling based on Modified Transfer Length Method (TLM) -- 2.5D Silicon Interposer Design in 40nm-Technology for 2D-IC and 3D-IC -- Conclusion and Future Wor

Atomistic simulations of nanoscale molecular and metal oxide junctions

The push to continually improve computing power through the further miniaturisation of electronic devices has led to an explosion of "post-Moore" technologies such as molecular electronics and quantum computing. The downscaling of electronic devices has enhanced the importance of quantum effects. As a result to aid in the understanding and development of new devices, accurate and efficient atomistic material modelling methods are crucial for guiding experiments. In this thesis first principle material modelling (e.g Density Functional Theory) is combined with the atomistic Non Equilibrium Green’s Function quantum transport method to study how the electronic structure of two interesting junction systems relate to the electron transport through the junction. These two types of junctions, molecular and metal oxide, have crucial roles to play in the development of molecular based memories and superconducting quantum computing respectively. The first half of this thesis shows how the electronic structure of Polyoxometalate molecules dominate their electron transport properties whilst their redox ability makes them promising for memory applications. The results of the simulations reveal how the charge-balancing counterions of Polyoxometalates increase the conductance of the molecular junctions by stabilisation of unoccupied states, this is a key discovery as the effect of counterions are typically ignored. Polyoxometalates can be altered easily by changing the identity of the central caged atom, enhancing device engineering possibilities. The IV characteristics and capacitance are computed for Polyoxometalates with different caged atoms, the results show how the charge transport and storage can be engineered by choice of caged species and redox state. In the second half of this work, the archetypal Josephson junction, Al/AlOx/Al is explored. The goal was to understand from an atomistic point of view how the nature of the amorphous barrier influences the electron transport. The calculations provide evidence that the oxide concentration of the amorphous barrier significantly influences the resistance of the junction, it is found that oxygen deficient barriers lead to higher than expected critical currents. Unexpectedly the simulations here fail to show an exponential relationship between barrier length and resistance of the device. It is argued that there is an effective barrier length smaller than the physical barrier length due to thinner regions of the barrier. This highlights how important an understanding of the atomic structure of these junctions are for designing high quality junctions for superconducting qubits