241 research outputs found
Online testing in ternary reversible logic
xii, 92 leaves : ill. ; 29 cmIn recent years ternary reversible logic has caught the attention of researchers because of its
enormous potential in different fields, in particular quantum computing. It is desirable that
any future reversible technology should be fault tolerant and have low power consumption;
hence developing testing techniques in this area is of great importance.
In this work we propose a design for an online testable ternary reversible circuit. The
proposed design can implement almost all of the ternary logic operations and is also capable
of testing the reversible ternary network in real time (online). The error detection unit is
also constructed in a reversible manner, which results in an overall circuit which meets
the requirements of reversible computing. We have also proposed an upgrade of the initial
design to make the design more optimized. Several ternary benchmark circuits have been
implemented using the proposed approaches. The number of gates required to implement
the benchmarks for each approach have also been compared. To our knowledge this is the
first such circuit in ternary with integrated online testability feature
Synthesis and testing of reversible Toffoli circuits
xii, 82 leaves : ill. ; 29 cmRecently, researchers have been interested in reversible computing because of its ability to
dissipate nearly zero heat and because of its applications in quantum computing and low
power VLSI design. Synthesis and testing are two important areas of reversible logic. The
thesis first presents an approach for the synthesis of reversible circuits from the exclusive-
OR sum-of-products (ESOP) representation of functions, which makes better use of shared
functionality among multiple outputs, resulting in up to 75% minimization of quantum cost
compared to the previous approach. This thesis also investigates the previous work on constructing
the online testable circuits and points out some design issues. A simple approach
for online fault detection is proposed for a particular type of ESOP-based reversible circuit,
which is also extended for any type of Toffoli circuits. The proposed online testable designs
not only address the problems of the previous designs but also achieve significant improvements
of up to 78% and 99% in terms of quantum cost and garbage outputs, respectively
The implementation and applications of multiple-valued logic
Multiple-Valued Logic (MVL) takes two major forms. Multiple-valued circuits can implement the logic directly by using multiple-valued signals, or the logic can be implemented indirectly with binary circuits, by using more than one binary signal to represent a single multiple-valued signal. Techniques such as carry-save addition can be viewed as indirectly implemented MVL. Both direct and indirect techniques have been shown in the past to provide advantages over conventional arithmetic and logic techniques in algorithms required widely in computing for applications such as image and signal processing.
It is possible to implement basic MVL building blocks at the transistor level. However, these circuits are difficult to design due to their non binary nature. In the design stage they are more like analogue circuits than binary circuits. Current integrated circuit technologies are biased towards binary circuitry. However, in spite of this, there is potential for power and area savings from MVL circuits, especially in technologies such as BiCMOS. This thesis shows that the use of voltage mode MVL will, in general not provide bandwidth increases on circuit buses because the buses become slower as the number of signal levels increases. Current mode MVL circuits however do have potential to reduce power and area requirements of arithmetic circuitry. The design of transistor level circuits is investigated in terms of a modern production technology. A novel methodology for the design of current mode MVL circuits is developed. The methodology is based upon the novel concept of the use of non-linear current encoding of signals, providing the opportunity for the efficient design of many previously unimplemented circuits in current mode MVL. This methodology is used to design a useful set of basic MVL building blocks, and fabrication results are reported. The creation of libraries of MVL circuits is also discussed.
The CORDIC algorithm for two dimensional vector rotation is examined in detail as an example for indirect MVL implementation. The algorithm is extended to a set of three dimensional vector rotators using conventional arithmetic, redundant radix four arithmetic, and Taylor's series expansions. These algorithms can be used for two dimensional vector rotations in which no scale factor corrections are needed. The new algorithms are compared in terms of basic VLSI criteria against previously reported algorithms. A pipelined version of the redundant arithmetic algorithm is floorplanned and partially laid out to give indications of wiring overheads, and layout densities. An indirectly implemented MVL algorithm such as the CORDIC algorithm described in this thesis would clearly benefit from direct implementation in MVL
Fault tolerance in reversible logic
In recent years reversible logic has offered a promising alternative to traditional logic circuits. Reversible logic introduces a mechanism which allows theoretically zero energy
dissipation by eliminating the possibility of information loss. However, it is also desirable
that all computation should ideally be done in a fault tolerant manner. To address this we
propose techniques to achieve fault tolerance in reversible logic based on a passive hardware redundancy technique. We propose two new designs for a reversible majority voter circuit that can be used to implement fault masking. Comparisons to existing designs are presented in terms of cost metrics such as gate count, garbage outputs, constant inputs, and quantum cost. Comparative failure probability analysis of the proposed voter circuits is also provided. Simulation results of the voter circuit failure probabilities over different numbers of trials are also presented. Our approach can be used to determine the circuit failure probability by using the gate failure probabilities. The proposed methodology can provide useful information for future reversible gate fabrication and designing future fault tolerant reversible circuits
An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit
Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature
Design and Simulation of Reversible Time Synchronized Quantum-Dot Cellular Automata Combinational Logic Circuits with Ultralow Energy
The quantum-dot cellular automata (QCA) represent emerging nanotechnology that is poised to supersede the current complementary metal-oxide-semiconductor digital integrated circuit technology. QCA constitutes an extremely promising transistor-less paradigm that can be downscaled to the molecular level, thereby facilitating tera-scale device integration and extremely low energy dissipation. Reversible QCA circuits, which have reversibility sustained down from the logical level to the physical level, can execute computing operations dissipating less energy than the Landauer energy limit (kBTln2). Time synchronization of logic gates is an essential additional requirement, especially in cases involving complex circuits, for ensuring accurate computational results. This paper reports the design and simulation of eight new both logically and physically reversible time-synchronized QCA combinational logic circuits. The new circuit design presented here mitigates the clock delay problems, which are caused by the non-synchronization of logic gate information, via the use of an inherently more symmetric circuit configuration. The simulation results confirm the behavior of the proposed reversible time-synchronized QCA combinational logic circuits which exhibit ultralow energy dissipation and simultaneously provide accurate computational results
Logic Synthesis for Established and Emerging Computing
Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported
- …