Design and experimental implementation of a hysteresis algorithm to optimize the maximum power point extracted from a photovoltaic system

In the several last years, numerous Maximum Power Point Tracking (MPPT) methods for photovoltaic (PV) systems have been proposed. An MPPT strategy is necessary to ensure the maximum power efficiency provided to the load from a PV module that is subject to external environmental perturbations such as radiance, temperature and partial shading. In this paper, a new MPPT technique is presented. Our approach has the novelty that it is a MPPT algorithm with a dynamic hysteresis model incorporated. One of the most cited Maximum Power Point Tracking methods is the Perturb and Observer algorithm since it is easily implemented. A comparison between the approach presented in this paper and the known Perturb and Observer method is evaluated. Moreover, a new PV-system platform was properly designed by employing low cost electronics, which may serve as an academical platform for further research and developments. This platform is used to show that the proposed algorithm is more efficient than the standard Perturb and Observer method.Peer ReviewedPostprint (published version

A flexible heterogeneous video processor system for television applications

A new video processing architecture for high-end TV applications is presented, featuring a flexible heterogeneous multi-processor architecture, executing video tasks in parallel and independently. The signal flow graph and the processors are programmable, enabling an optimal picture quality for different TV display modes. The concept is verified by an experimental chip design. The architecture allows several video streams to be processed and displayed in parallel and in a programmable way, with an individual signal qualit

Design And Analysis Of A Fast Transient Voltage Regulator With All Ceramic Output Capacitors For Mobile Microprocessors

Keperluan untuk mereka bentuk pengatur voltan yang mempunyai tindak balas transien yang cepat didorong oleh kadar transien yang semakin meningkat daripada mikropemproses mudah alih. Oleh itu, mengoptimumkan frekuensi pensuisan pengatur voltan menjadi langkah penting untuk mencapai keseimbangan antara mengekalkan kecekapan pengatur voltan dan meningkatkan tindak balas transien. Kapasitor seramik berlapis telah menjadi lebih popular sebagai kapasitor output pengantara voltan disebabkan oleh saiznya yang kecil dan kos murah. Walaupun topologi penukar buck kekal tidak berubah betahun-tahun, terdapat banyak inovasi dan kejayaan cemerlang dalam peringkat kuasa pengatur voltan dan teknologi kawalan. Selain itu, reka bentuk yang berorientasikan galangan keluaran dan AVP (Penempatan Voltan Automatik) telah diperkenalkan untuk menangani keperluan transien. Banyak kajian juga memberi tumpuan untuk meningkatkan kecekapan pegantara voltage terutama untuk system yang beroperasi dengan bateri. Sebuah pengatur voltan bertindak balas laju yang mempunyai hanya kapasitor output seramik untuk mikropemproses mudah alih dicadangkan dalam kajian ini. Hasil kajian ini menunjukkan bahawa pengatur voltan yang direka adalah stabil dengan jenis dan bilangan kapasitor seramik berlapisan yang dicadangkan. Lebih penting lagi, keputusan transien juga adalah sehampir dengan keputusan simulasi di mana output pengantara voltan tidak mengalami kelanjakan dan kejatuhan voltan semasa dimuatkan dengan arus dinamik yang bermaknitud 10.5A dalam 1μs. Kesimpulannya, sebuah pengatur voltan dengan tindak balas laju yang mempunyai hanya kapasitor output seramik telah direka dan dianalisis and ia mempunyai tindak balas transien yang lebih baik berbanding dengan reka bentuk asal. Keperluan untuk mereka bentuk pengatur voltan yang mempunyai tindak balas transien yang cepat didorong oleh kadar transien yang semakin meningkat daripada mikropemproses mudah alih. Oleh itu, mengoptimumkan frekuensi pensuisan pengatur voltan menjadi langkah penting untuk mencapai keseimbangan antara mengekalkan kecekapan pengatur voltan dan meningkatkan tindak balas transien. Kapasitor seramik berlapis telah menjadi lebih popular sebagai kapasitor output pengantara voltan disebabkan oleh saiznya yang kecil dan kos murah. Walaupun topologi penukar buck kekal tidak berubah betahun-tahun, terdapat banyak inovasi dan kejayaan cemerlang dalam peringkat kuasa pengatur voltan dan teknologi kawalan. Selain itu, reka bentuk yang berorientasikan galangan keluaran dan AVP (Penempatan Voltan Automatik) telah diperkenalkan untuk menangani keperluan transien. Banyak kajian juga memberi tumpuan untuk meningkatkan kecekapan pegantara voltage terutama untuk system yang beroperasi dengan bateri. Sebuah pengatur voltan bertindak balas laju yang mempunyai hanya kapasitor output seramik untuk mikropemproses mudah alih dicadangkan dalam kajian ini. Hasil kajian ini menunjukkan bahawa pengatur voltan yang direka adalah stabil dengan jenis dan bilangan kapasitor seramik berlapisan yang dicadangkan. Lebih penting lagi, keputusan transien juga adalah sehampir dengan keputusan simulasi di mana output pengantara voltan tidak mengalami kelanjakan dan kejatuhan voltan semasa dimuatkan dengan arus dinamik yang bermaknitud 10.5A dalam 1μs. Kesimpulannya, sebuah pengatur voltan dengan tindak balas laju yang mempunyai hanya kapasitor output seramik telah direka dan dianalisis and ia mempunyai tindak balas transien yang lebih baik berbanding dengan reka bentuk asal. ________________________________________________________________________________________________________________________ The need to have fast transient response of the voltage regulator is driven by the increasing current slew rate of the mobile microprocessor. Hence, optimizing the switching frequency of the voltage regulator becomes an important step to achieve a balance between preserving the efficiency of the voltage regulator and improving the transient response. Besides, output capacitor solution with multilayer ceramic capacitor has also become more popular due to its small size and cheap cost. Over the years, even though the topology of the buck converter remains unchanged, there are plenty of innovations and breakthroughs in the power stage of the voltage regulator and controller technology. In addition, output impedance oriented design and adaptive voltage positioning (AVP) feature are also introduced to address the transient requirements. Apart from improving the dynamic response of the voltage regulator, many research works also focus on improving the efficiency of the voltage regulator, especially for battery-powered systems. A fast transient voltage regulator with all ceramic output capacitors for mobile microprocessor is proposed in this study. The outcome of the study shows that the voltage regulator designed is stable with the proposed type and number of multilayer ceramic capacitors. More importantly, the actual transient results correlate well with the simulation results where minimal transient droop and overshoot are observed with a dynamic current load step with a slew rate of 10.5A per 1 μs. In conclusion, a fast transient voltage regulator with all ceramic output capacitors is designed and analyzed which proven to have better transient performance compared to the original design on the test boar

Information Management for Smart and Sustainable Mobility

The main objective of this work is to present a modular platform to manage traffic information for smart mobility. The management and collection of dynamic data is a challenging process especially in the context of low penetration of floating car data (FCD) and limited availability of traffic monitoring stations. In this work, three different road segments of a European medium-sized city were selected to collect vehicle dynamic data over multiple scenarios of traffic demand. Simultaneously, traffic volumes were recorded in real time. The main objective of this pilot experiment was to assess how it would be possible to read and predict traffic congestion and emissions levels with limited information and how data from multiple sources should be managed in order to correlate and deal with this information in real time. It was possible to correlate simultaneously multiple data set such as congestion values, specific vehicle power (VSP) mode distribution, Google traffic data and emission. Preliminary findings suggest that in urban arterials travel time and congestion levels can be reliable indicators for estimating emissions in real time. In sections of rural arterials, the estimation of real-time traffic performance is more complex. Key issues towards the implementation of a prototyping platform in an urban context are also discusse

Digital Circuit Design Using Floating Gate Transistors

Floating gate (flash) transistors are used exclusively for memory applications today. These applications include SD cards of various form factors, USB flash drives and SSDs. In this thesis, we explore the use of flash transistors to implement digital logic circuits. Since the threshold voltage of flash transistors can be modified at a fine granularity during programming, several advantages are obtained by our flash-based digital circuit design approach. For one, speed binning at the factory can be controlled with precision. Secondly, an IC can be re-programmed in the field, to negate effects such as aging, which has been a significant problem in recent times, particularly for mission-critical applications. Thirdly, unlike a regular MOSFET, which has one threshold voltage level, a flash transistor can have multiple threshold voltage levels. The benefit of having multiple threshold voltage levels in a flash transistor is that it allows the ability to encode more symbols in each device, unlike a regular MOSFET. This allows us to implement multi-valued logic functions natively. In this thesis, we evaluate different flash-based digital circuit design approaches and compare their performance with a traditional CMOS standard cell-based design approach. We begin by evaluating our design approach at the cell level to optimize the design’s delay, power energy and physical area characteristics. The flash-based approach is demonstrated to be better than the CMOS standard cell approach, for these performance metrics. Afterwards, we present the performance of our design approach at the block level. We describe a synthesis flow to decompose a circuit block into a network of interconnected flash-based circuit cells. We also describe techniques to optimize the resulting network of flash-based circuit cells using don’t cares. Our optimization approach distinguishes itself from other optimization techniques that use don’t cares, since it a) targets a flash-based design flow, b) optimizes clusters of logic nodes at once instead of one node at a time, c) attempts to reduce the number of cubes instead of reducing the number of literals in each cube and d) performs optimization on the post-technology mapped netlist which results in a direct improvement in result quality, as compared to pre-technology mapping logic optimization that is typically done in the literature. The resulting network characteristics (delay, power, energy and physical area) are presented. These results are compared with a standard cell-based realization of the same block (obtained using commercial tools) and we demonstrate significant improvements in all the design metrics. We also study flash-based FPGA designs (both static and dynamic), and present the tradeoff of delay, power dissipation and energy consumption of the various designs. Our work differs from previously proposed flash-based FPGAs, since we embed the flash transistors (which store the configuration bits) directly within the logic and interconnect fabrics. We also present a detailed description of how the programming of the configuration bits is accomplished, for all the proposed designs