DESIGN AND PERFORMANCE ANALYSIS OF FULL ADDER USING 6-T XOR–XNOR CELL

In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product)

64 x 64 Bit Multiplier Using Pass Logic

ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works

Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

In this paper a new full adder is proposed The number of Transistors used in the proposed full adder is 13 Average leakage is 62 of conventional 28 transistor CMOS full adder The leakage power reduction results in overall power reduction The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tool

Hybrid memristor-CMOS implementation of logic gates design using LTSpice

In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area

Method to analyze the influence of hysteresis in optical arithmetic units

A new method to analyze the influence of possible hysteresis cycles in devices employed for optical computing architectures is reported. A simple full adder structure is taken as the basis for this method. Single units, called optical programmable logic cells, previously reported by the authors, compose this structure. These cells employ, as basic devices, on-off and SEED-like components. Their hysteresis cycles have been modeled by numerical analysis. The influence of the different characteristic cycles is studied with respect to the obtained possible errors at the output. Two different approaches have been adopted. The first one shows the change in the arithmetic result output with respect to the different values and positions of the hysteresis cycle. The second one offers a similar result, but in a polar diagram where the total behavior of the system is better analyzed

An approach to component generation and technology adaptation

Component generation is the task of mapping the abstract functional specification of register-transfer (RT) components, such as decoders and multiplexers, adders and comparators, and multipliers and arithmetic logic units, into configurations of connected physical layout cells. Cells are drawn from a given ASIC (application-specific integrated circuit) library.In this dissertation, I describe a symbolic pattern-matching approach to component generation and, relative to this, an approach to automating technology adaptation. I define the component decomposition algorithm and technology compilation algorithm that formalize these two approaches and describe implementations of each, in the DTAS component generation system and the LOLA technology adaptation system, respectively. I present empirical results to validate the utility of my approach to component generation, and I present a demonstration to validate my approach to technology adaptation.My approach to component generation has two significant benefits. First, it enables the use of complex functional library cells, such as adders and CLAs, in the generation of designs for functional units. Second, it effectively searches the design space for designs that make desirable tradeoffs between design constraints, such as area and delay. My approach to technology adaptation is significant because it bootstraps the DTAS component generation system into new ASIC cell libraries, as well as cell libraries as they undergo change. In this way, the technology compilation algorithm automates the task of maintaining technology independence.To validate my approach to component generation, I present the results of four sets of experiments using the DTAS component generation system. The first set examines the effectiveness of search control in DTAS; the second examines the capability to find desirable design alternatives; the third compares designs generated by DTAS with those of MISII; and the fourth shows how the use of complex library cells improves design quality. To validate my approach to automating technology adaptation, I demonstrate the application of the LOLA technology adaptation system to a cell library as it undergoes four phases of evolution

New Approaches for Memristive Logic Computations

Over the past five decades, exponential advances in device integration in microelectronics for memory and computation applications have been observed. These advances are closely related to miniaturization in integrated circuit technologies. However, this miniaturization is reaching the physical limit (i.e., the end of Moore\u27s Law). This miniaturization is also causing a dramatic problem of heat dissipation in integrated circuits. Additionally, approaching the physical limit of semiconductor devices in fabrication process increases the delay of moving data between computing and memory units hence decreasing the performance. The market requirements for faster computers with lower power consumption can be addressed by new emerging technologies such as memristors. Memristors are non-volatile and nanoscale devices and can be used for building memory arrays with very high density (extending Moore\u27s law). Memristors can also be used to perform stateful logic operations where the same devices are used for logic and memory, enabling in-memory logic. In other words, memristor-based stateful logic enables a new computing paradigm of combining calculation and memory units (versus von Neumann architecture of separating calculation and memory units). This reduces the delays between processor and memory by eliminating redundant reloading of reusable values. In addition, memristors consume low power hence can decrease the large amounts of power dissipation in silicon chips hitting their size limit. The primary focus of this research is to develop the circuit implementations for logic computations based on memristors. These implementations significantly improve the performance and decrease the power of digital circuits. This dissertation demonstrates in-memory computing using novel memristive logic gates, which we call volistors (voltage-resistor gates). Volistors capitalize on rectifying memristors, i.e., a type of memristors with diode-like behavior, and use voltage at input and resistance at output. In addition, programmable diode gates, i.e., another type of logic gates implemented with rectifying memristors are proposed. In programmable diode gates, memristors are used only as switches (unlike volistor gates which utilize both memory and switching characteristics of the memristors). The programmable diode gates can be used with CMOS gates to increase the logic density. As an example, a circuit implementation for calculating logic functions in generalized ESOP (Exclusive-OR-Sum-of-Products) form and multilevel XOR network are described. As opposed to the stateful logic gates, a combination of both proposed logic styles decreases the power and improves the performance of digital circuits realizing two-level logic functions Sum-of-Products or Product-of-Sums. This dissertation also proposes a general 3-dimentional circuit architecture for in-memory computing. This circuit consists of a number of stacked crossbar arrays which all can simultaneously be used for logic computing. These arrays communicate through CMOS peripheral circuits

ALL-OPTICAL FREQUENCY ENCODED DIBIT-BASED PARITY GENERATOR USING REFLECTIVE SEMICONDUCTOR OPTICAL AMPLIFIER WITH SIMULATIVE VERIFICATION

High-speed signal computation and communication are an essential part of modern communication that increases optical necessity. Therefore, researchers developed different types of digital devices in the all-optical domain. Due to the versatile gain medium of reflective semiconductor optical amplifiers (RSOAs), it has various important applications in passive optical networks. In comparison with semiconductor optical amplifier (SOA), RSOAs exhibit better gain performance because of their double pass property. Therefore, RSOA shows better switching properties. In this communication, co-propagation scheme of RSOA is used to design and analyze a frequency encoded dibit-based parity generator. Taking the advantages of RSOA like high switching speed, low noise, high gain, and low power consumption, the proposed design achieves these qualities. This design simulated in MATLAB and simulated outputs accurately verify the truth table