Architectures for Adaptive Low-Power Embedded Multimedia Systems

This Ph.D. thesis describes novel hardware/software architectures for adaptive low-power embedded multimedia systems. Novel techniques for run-time adaptive energy management are proposed, such that both HW & SW adapt together to react to the unpredictable scenarios. A complete power-aware H.264 video encoder was developed. Comparison with state-of-the-art demonstrates significant energy savings while meeting the performance constraint and keeping the video quality degradation unnoticeable

Towards Computational Efficiency of Next Generation Multimedia Systems

To address throughput demands of complex applications (like Multimedia), a next-generation system designer needs to co-design and co-optimize the hardware and software layers. Hardware/software knobs must be tuned in synergy to increase the throughput efficiency. This thesis provides such algorithmic and architectural solutions, while considering the new technology challenges (power-cap and memory aging). The goal is to maximize the throughput efficiency, under timing- and hardware-constraints

An application specific low bit-rate video compression system geared towards vehicle tracking.

Thesis (M.Sc.Eng.)-University of Natal, Durban, 2003.The ability to communicate over a low bit-rate transmission channel has become the order of the day. In the past, transmitted data over a low bit-rate transmission channel, such as a wireless link, has typically been reserved for speech and data. However, there is currently a great deal of interest being shown in the ability to transmit streaming video over such a link. These transmission channels are generally bandwidth limited hence bit-rates need to be low. Video on the other hand requires large amounts of bandwidth for real-time streaming applications. Existing Video Compression standards such as MPEG-l/2 have succeeded in reducing the bandwidth required for transmission by exploiting redundant video information in both the spatial and temporal domains. However such compression systems are geared towards general applications hence they tend not to be suitable for low bit-rate applications. The objective of this work is to implement such a system. Following an investigation in the field of video compression, existing techniques have been adapted and integrated into an application specific low bit-rate video compression system. The implemented system is application specific as it has been designed to track vehicles of reasonable size within an otherwise static scene. Low bit-rate video is achieved by separating a video scene into two areas of interest, namely the background scene and objects that move with reference to this background. Once the background has been compressed and transmitted to the decoder, the only data that is subsequently transmitted is that that has resulted from the segmentation and tracking of vehicles within the scene. This data is normally small in comparison with that of the background scene and therefore by only updating the background periodically, the resulting average output bit-rate is low. The implemented system is divided into two parts, namely a still image encoder and decoder based on a Variable Block-Size Discrete Cosine Transform, and a context-specific encoder and decoder that tracks vehicles in motion within a video scene. The encoder system has been implemented on the Philips TriMedia TM-1300 digital signal processor (DSP). The encoder is able to capture streaming video, compress individual video frames as well as track objects in motion within a video scene. The decoder on the other hand has been implemented on the host PC in which the TriMedia DSP is plugged. A graphic user interface allows a system operator to control the compression system by configuring various compression variables. For demonstration purposes, the host PC displays the decoded video stream as well as calculated rate metrics such as peak signal to noise ratio and resultant bit-rate. The implementation of the compression system is described whilst incorporating application examples and results. Conclusions are drawn and suggestions for further improvement are offered

Etude et implantation d'algorithmes de compression d'images dans un environnement mixte matériel et logiciel

Le sujet de cette thèse est la contribution au développement et à la conception d’un système multimédia embarqué en utilisant la méthodologie de conception conjointe logicielle/matérielle (codesign). Il en a découlé la constitution d’une bibliothèque des modules IP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateforme matérielle d’acquisition et de restitution vidéo a été réalisée servant de préalable à l’évaluation de la méthodologie de conception en codesign et à toute étude d’algorithme de traitement vidéo. On s’est intéressé en particulier à l’étude et à l’implantation de la norme de compression vidéo H.263 de l’organisme UIT-T. La fréquence de fonctionnement de la plateforme est de 120 MHz. L’ensemble du développement est exécuté par le processeur NIOS II sous le système d’exploitation μClinux. Le codeur H.263 ainsi développé, grâce aux différents accélérateurs matériels pour le SAD, TCD/TCDI et Q/QI permet de coder des séquences vidéo [email protected] main purpose of this thesis was to contribute to the development and to the design of an embedded system for multimedia by using the HW/SW methodology (codesign). A library of flexible IP cores (Intellectual Property) for video applications was created. Within this framework, a hardware platform for video acquisition and video restitution was achieved in order to evaluate the codesign methodology approach and to study the video processing algorithm. We have studied and implemented the H.263 video encoder from the UIT-T organism. The frequency of our platform is about 120 MHz. The whole development was executed under μClinux Operating System and controlled by the NIOS II processor. The H.263 encoder was developed with different hardware accelerators for the SAD, TCD/TCDI and Q/QI operations and permits finally to code video sequences at QCIF@15Hz

Etude et Implantation d'Algorithmes de Compression d'Images dans un Environnement Mixte Matériel et Logiciel

The main purpose of this thesis was to contribute to the development and to the design of anembedded system for multimedia by using the HW/SW methodology (codesign). A library offlexible IP cores (Intellectual Property) for video applications was created. Within thisframework, a hardware platform for video acquisition and video restitution was achieved inorder to evaluate the codesign methodology approach and to study the video processingalgorithm. We have studied and implemented the H.263 video encoder from the UIT-Torganism. The frequency of our platform is about 120 MHz. The whole development wasexecuted under μClinux Operating System and controlled by the NIOS II processor. TheH.263 encoder was developed with different hardware accelerators for the SAD, TCD/TCDIand Q/QI operations and permits finally to code video sequences at [email protected] sujet de cette thèse est la contribution au développement et à la conception d’un systèmemultimédia embarqué en utilisant la méthodologie de conception conjointelogicielle/matérielle (codesign). Il en a découlé la constitution d’une bibliothèque des modulesIP (Intellectual Property) pour les applications vidéo. Dans ce contexte, une plateformematérielle d’acquisition et de restitution vidéo a été réalisée servant de préalable àl’évaluation de la méthodologie de conception en codesign et à toute étude d’algorithme detraitement vidéo. On s’est intéressé en particulier à l’étude et à l’implantation de la norme decompression vidéo H.263 de l’organisme UIT-T. La fréquence de fonctionnement de laplateforme est de 120 MHz. L’ensemble du développement est exécuté par le processeurNIOS II sous le système d’exploitation μClinux. Le codeur H.263 ainsi développé, grâce auxdifférents accélérateurs matériels pour le SAD, TCD/TCDI et Q/QI permet de coder desséquences vidéo QCIF@15Hz

System-level power optimization:techniques and tools

This tutorial surveys design methods for energy-efficient system-level design. We consider electronic sytems consisting of a hardware platform and software layers. We consider the three major constituents of hardware that consume energy, namely computation, communication, and storage units, and we review methods of reducing their energy consumption. We also study models for analyzing the energy cost of software, and methods for energy-efficient software design and compilation. This survery is organized around three main phases of a system design: conceptualization and modeling design and implementation, and runtime management. For each phase, we review recent techniques for energy-efficient design of both hardware and software